🚀 go-pugleaf

Hello net-working users!

I am working on a VLSI module generator, which includes automatic
layout design of static CMOS complex gates. I would like to
know, whether there exists a software solution to break some
high level circuit description into a gate level description, which

a) uses complex gates of a given library,

or

b) 'invents' those complex gates, which leads to a minimal gate count
   of the circuit.

Any experience or pointers?


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 Ronald Hindmarsh                      e-mail: ronald@cs.tu-berlin.de
 Institut fuer Technische Informatik
 TU Berlin FR 3-9
 Franklinstr. 29                            Phone: (+49) 30 314-73432
 W-1000 Berlin 10                             Fax: (+49) 30 314-21103
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