Article View: comp.lsi
Article #265Need gate level logic simulator
From: From: siu (Denny Siu)
Date: Tue, 10 Jul 1990 00:28
Date: Tue, 10 Jul 1990 00:28
13 lines
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941 bytes
Summary: Expires: References: <1990Jun18.025334.7298@monu6.cc.monash.edu.au> <14012@venera.isi.edu> <24@pubit.sublink.ORG> Sender: Reply-To: siu@fnrsun.Data-IO.COM (Denny Siu) Followup-To: Distribution: Organization: Data-IO Corporation; Redmond, WA Keywords: Does anyone know about any public domain gate level logic simulator that can handle unit time delay. The primitive should not lower than AND or OR gate. Can Csim or Rsim do the job, or they are tranistor level simulator? Thank you in advance!
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rutgers!ucsd!swrinde!zaphod.mps.ohio-state.edu!samsung!uunet!pilchuck!dataio!siuShow Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rutgers!ucsd!swrinde!zaphod.mps.ohio-state.edu!samsung!uunet!pilchuck!dataio!siu From: siu@Data-IO.COM (From: siu@fnrsun.Data-IO.COM (Denny Siu)) Newsgroups: comp.lsi,comp.lsi.cad,sci.electronics Subject: Need gate level logic simulator Message-ID: <2567@dataio.Data-IO.COM> Date: 10 Jul 90 00:28:47 GMT Sender: news@Data-IO.COM Followup-To: comp.lsi Lines: 13