🚀 go-pugleaf

In article <12363@encore.Encore.COM> jcallen@encore.com (Jerry Callen) writes:
+---------------
| Does anyone KNOW if Verilog HDL is VHSIC HDL?
+---------------

No, "Verilog HDL" != VHSIC HDL, but VHSIC == "VHDL". And indeed, Verilog HDL
and VHDL are the two main current contenders for hardware behavioral models
intended for "compiling" into gates using some form of logic synthesis.

From what I can tell with the ASIC vendors I've been talking to, synthesis
from Verilog HDL is here "now" (plus or minus a beta test or so), and syn-
thesis from VHDL is promised anywhere from "someday" to "real soon" to "as
soon as we get the Verilog HDL synthesis software stable".

Or to put it another way, "everybody" says VDHL is "the future" and "the way
to go" and "required, if you want any government business", but synthesis from
a Verilog HDL model is here now.

The Verilog simulator itself [the program product from Cadence] is certainly
here now, and you can sometimes get even non-ASIC chip vendors to give you
[o.k., often under NDA] Verilog behavioral descriptions for their chips,
which makes it a lot easier to simulate a board or a system with a mix of
standard parts and your custom parts. And wouldn't you know it, those same
chip vendors that are so happy to give you the Verilog models for their chips
somehow haven't yet gotten around to writing VHDL models for their chips...
which is no surprise since most of the big chip vendors use Verilog internally!

And of course, synthesis from either Verilog or VHDL functional and gate-level
models has been around for a while (though even here Verilog seems to be more
common).


-Rob

p.s. Definition of some terms [to the best of my understanding, may be a
little bit "off", I'm still learning this stuff]:

"Behavioral model" - a high-level almost black-box description of the
relationships between a module's inputs, outputs, and possibly some internal
state. In Verilog HDL and in VHDL, one uses "C"-like variables, operators,
and flow control primitives. Delays and timing and synchronization may be
handled explicitly in the model, or you may choose to do a "zero-delay" model,
for more simulation speed. Parallel processes are explicitly supported, as
are fork/join, events/wait_for_event, etc.

"Functional model" - all you are allowed to do is interconnect instantiations
of pre-defined sub-modules from a library, usually provided by a third party
CAD software firm. At this level, you might have "counters", "ALUs", "RAMs",
"buffers", etc. (When doing board-level functional modelling, these might be
chips, e.g. 74F374.) Each library is tuned to a specific ASIC vendor or silicon
foundry, and each predefined element accurately reflects the drive, delays,
etc., of some "standard cell" (or in the case of gate arrays, pre-defined
allocation/interconnection) that achieves that functionality.

"Gate-level model" - all you are allowed to do is to specify the interconnects
between instantiations of pre-defined low-level "gate" constructs, like AND,
OR, NOR, XOR, transmission gate, pull-up, wire (of various capacitances), etc.
All higher-level functionality must be expressed in terms of wires and gates.
Delays, drive capacity, wire capacitance, etc., are all explicit at this level.

"Synthesis" - the automatic transformation or "compiling" of a behavioral or
functional model into a gate-level model, possibly with considerable optim-
ization.

[Gate-level models thus correspond to the "assembly language" of ASIC design,
and "assembly" would thus include transforming the gate-level design into the
primitive rectangles that make up transistors in silicon, and the placing of
the transistors and routing of "wires" (other rectangles of silicon and alum-
inum) between them.]

-----
Rob Warnock, MS-9U/510		rpw3@sgi.com		rpw3@pei.com
Silicon Graphics, Inc.		(415)335-1673		Protocol Engines, Inc.
2011 N. Shoreline Blvd.
Mountain View, CA  94039-7311