🚀 go-pugleaf

 keithl@loop.uucp (Keith Lofstrom;;;628-3645) writes:
>
>Vendors seem unnecessarily reticent about quoting prices publically;  can
>anyone think of a good way to collect this data without angering them?
>
>

I sympathize. I went through this silliness about 2 years ago. I just asked
them for quotes on several die sizes in the same package. You can get a couple
of data points and then assume price is directly proportional to yield. Then,
I plotted yield vs. size assuming Poisson distribution, and again using Seed's
algorithm. By the way, when I say yield, I mean the total number of good die
per wafer, not just the percentage of good die. Thus, you need to estimate
the number of die/wafer. For a given technology, cost/wafer is basically fixed.

But, you can pit 2 vendors against eachother. Vendor 'L' would quote one price,
then vendor 'V' would quote a lower one, both vendors knowing that they were
competing against eachother. I told vendor 'L' that vendor 'V' was cheaper.
Vendor 'L' would ask, "Well, what did they bid ?". I'd say, "Well, I can't
tell you the exact price, but it's between $18.43 and $18.45 per chip". This
would go on for a few iterations.

. . .

For gate arrays and standard cells, you will find lower prices from Japanese
companies, but you will find that their macrocell libraries aren't as highly
developed as U.S. vendors. All vendors have the same basic cell libraries
(flip-flops, gates, muxes, and decoders), but differ wildly on things like
multipliers, CPU's, UARTS, etc.

Many vendors will provide design 'kits' which let you use Daisy, ViewLogic,
or other schematic capture packages for design entry. Be careful. I have
ALWAYS seen problems during database conversion. Another hassle is back-
annotation of layout delays, etc. It's probably cheaper to use a 'design kit'
but it's more hassle than using the vendor's CAD tools. An alternative is to
do work inside the vendor's design center. I strongly recommend this approach
if (a) It's the first design with the vendor, and (b) you are considering
purchasing their tools. Some vendors will loan their tools free of charge for
a 'test drive', especially if you book a design with them.

I'm a bit reluctant to name vendors because there are so many out there which
I haven't used, but have outstanding reputations. Here are the ones I have
worked with:

LSI Logic - Very picky with design signoff, but once this step is reached,
you will have a chip with no surprises. Definitely a WYSIWYG (what-you-
simulate-is-what-you-get) vendor. Good toolset. Somewhat higher in price.

VLSI Technology - More flexible than LSI Logic, slightly better toolset, and
slightly lower price.

National Semiconductor - Used as a 'fab for hire', ie "here's my PG tape, now
give me my wafers". Aggressive pricing.

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