🚀 go-pugleaf

Dear all,

I would like to know the present state regarding a formal definition
for a subset of VHDL aiming at synthesis.

I believe there is a group (VHDL Synthesis Working Group in Europe???) that
is trying to specify this subset.

Does anybody know how I can get info on this subject?

Thanks a lot,

Meyer.

PS: I will summarise to the group the responses I get on this
+--------------------------+-----------------------------------------------+
|Meyer Elias Nigri         |   JANET:mnigri@uk.ac.ucl.cs                   |
|Dept. of Computer Science |  BITNET:mnigri%uk.ac.ucl.cs@UKACRL            |
|University College London |Internet:mnigri%cs.ucl.ac.uk@nsfnet-relay.ac.uk|
|Gower Street              | ARPANet:mnigri@cs.ucl.ac.uk                   |
|London WC1E 6BT           |    UUCP:...!mcvax!ukc!ucl-cs!mnigri           |
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|Tel: +44 71 387-7050      | Fax: +44 71 387-1397    |    Telex: 28722     |
|                 ext. 3708|                         |                     |
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