🚀 go-pugleaf

In article <3201@ucl-cs.uucp>, M.Nigri@cs.ucl.ac.uk (Meyer E. Nigri) writes:
|> 
|> Dear all,
|> 
|> I would like to know the present state regarding a formal definition
|> for a subset of VHDL aiming at synthesis.
|> 
|> I believe there is a group (VHDL Synthesis Working Group in Europe???) that
|> is trying to specify this subset.
|> 
|> Does anybody know how I can get info on this subject?
|> 
|> Thanks a lot,
|> 
|> Meyer.
|> 
|> PS: I will summarise to the group the responses I get on this

Hi,

You might want to take a look at the following :

VHDL for Simulation, Synthesis and Formal Proofs of Hardware, edited by Jean
Mermet (Kluwer Academic Publishers).  This is a collection of papers, some of
which might be of interest to you.

Towards the Correct Synthesis of VHDL Specifications, PhD dissertation of 
Xinning Wang, ECE department Syracuse University.

-Yegna.

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The contents of this article are the author's own views - they do not 
represent the view of any organisation such as the CASE centre or 
Syracuse University.

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# Yegnashankar Parasuram.						#
# Graduate Student at CE Department of Syracuse University.		#
# Office  : 2-128, Centre for Science & Technology.			#
# email   : yegna@cat.syr.edu.						#
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