Verilog test vectors into LSI .TPT and .SCL files anyone ?

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Article #445

#445

From: U.N.Owen
Date: Tue, 18 Dec 1990 01:28

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Hi folks,

	(I hope this is the right group for this question...)

		Anyone know of a way to convert verilog simulations
	into LSI ASIC test vector files (TPT and SCL)?

	Please email... 
Thanks

-- 
...ames!vsi1!v7fs1!U.N.Owen    **** Aunt Agatha  Where are you ? :-) ********

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From: U.N.Owen@hsv3.UUCP (U.N.Owen)
Newsgroups: comp.lsi
Subject: Verilog test vectors into LSI .TPT and .SCL files anyone ?
Message-ID: <6294@hsv3.UUCP>
Date: 18 Dec 90 01:28:24 GMT
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