Article View: comp.lsi
Article #456SIS logic optimizer
From: Dirk Naumann
Date: Mon, 07 Jan 1991 17:13
Date: Mon, 07 Jan 1991 17:13
11 lines
843 bytes
843 bytes
Does anybody know the stage of development of the logic optimizer SIS, which is supposed to do logic circuit optimization for sequential circuits ? Thanks in advance -- Dirk Naumann naumann@eng.buffalo.edu, ECE Department, SUNY at Buffalo
Technical Details
Message-ID:
<53652@eerie.acsu.Buffalo.EDU>Path:
arc1-ca.pugleaf.net!utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!ub!naumannShow Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!ub!naumann From: naumann@autarch.acsu.buffalo.edu (Dirk Naumann) Newsgroups: comp.lsi,comp.lsi.cad Subject: SIS logic optimizer Message-ID: <53652@eerie.acsu.Buffalo.EDU> Date: 7 Jan 91 17:13:02 GMT Sender: news@acsu.Buffalo.EDU Reply-To: naumann@autarch.acsu.buffalo.edu (Dirk Naumann) Followup-To: comp.lsi Organization: SUNY Buffalo, Academic Computing Services Lines: 11 Nntp-Posting-Host: autarch.acsu.buffalo.edu Originator: naumann@autarch.acsu.buffalo.edu