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Article #608yield estimation in digital CMOS VLSI
From: Brad Carlson
Date: Wed, 23 Dec 1992 19:53
Date: Wed, 23 Dec 1992 19:53
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Please reply to bcarlson@sbee.sunysb.edu Can anybody tell me if a model exists for the distribution of the delay of a digital CMOS VLSI circuit as a function of process parameter variation? That is, given the nominal delay of a circuit, I want to estimate the yield for a given operating frequency. References to articles describing such a model are sufficient. Thanks in advance, Brad Carlson SUNY Stony Brook
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Newsgroups: comp.lsi,comp.lsi.cad Path: arc1-ca.pugleaf.net!sparky!uunet!psinntp!newstand.syr.edu!lynx.cat.syr.edu!bcarlson From: bcarlson@lynx.cat.syr.edu (Brad Carlson) Subject: yield estimation in digital CMOS VLSI Message-ID: <1992Dec23.145317.19667@newstand.syr.edu> Organization: Syracuse University Date: Wed, 23 Dec 92 14:53:17 EST Lines: 11