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 The First Annual ISSCC Short Course
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INTRODUCTION to COMPUTER ARCHITECTURE

February 23, 1993
San Francisco Marriott Hotel

Course Objective: This course is a tutorial on computer architecture.
No prior knowledge of the subject is assumed.  Upon completion of the
course the attendee will understand the basic issues facing the
computer architect as well as the likely directions of future computer
architectural developments.

Who Should Take This Course: Individuals with little or no background
in computer architecture who are working in design or managing design
of microprocessor components or systems.

Course Outline:
      Overview (Jouppi)
Introduction: (Storage Hierarchy Overview, Bandwidth vs.  Latency
Performance Equation, Amdahl's Law). Instruction-Set Architectures
(Load Store vs.  Memory, Memory Addressing, RISC vs. CISC Case Study).
Micro Architecture (Datapaths, Pipelining, Hazards and Interlocks,
Interrupts and Traps). System Issues (I/O; Disks and Networks,
Busses).

      Memory Hierarchy Design (Przybylski)
Performance Revisited. Cache Design Basics. Organization (Miss Ratio
vs.  Cache Size, Set Associativity and Block Size). Impact of Cache
Design (Performance vs.  Size and Associatively). On-Chip Cache Design
Issues. Secondary Cache Issues. Virtual Memory (Address Translation
Basics, Translation) Lookaside Buffer (TLB), TLB and Cache
Interaction).

      SuperScaler and Parallel Processors (Horowitz)
Machine Performance (Good RISC CPI, Pushing CPI below 1). Instruction,
Loop and Task-Level Parallelism. SuperScaler Design (Structure,
Instruction Fetch/Issue, Speedups and Complexities).
Parallel Processors (Vector, Distributed and Shared Memory Machines).

The Instructors:
Norman P. Jouppi received BSEE and MSEE from Northwestem University in
1979 and 1980, respectively.  He received the PhD in Electrical
Engineering from Stanford University in 1984. Since 1984, he has been
a member of research staff, DEC Western Research Lab and a Consulting
Assistant Professor in the Stanford EE Department. From 1981 to 1984
he was a principal architect and implementor of the MIPS processor at
Stanford. From 1985 to 1988 he was the principal architect and
implementor of the MultiTitan CPU. His current research includes
computer architecture, VLSI design, BiCMOS circuit design, and VLSI
CAD tools.

Steven Przybylski is a consultant on system architecture, product
planning, and memory hierarchy.  He received a BASc from the
University of Toronto in 1980 and the MSEE and PhD from Stanford in
1988 and 1982, respectively. At Stanford, he designed much of the
original MIPS microprocessor.  His PhD research was on cache and
memory hierarchy design.  He has written a book and numerous papers on
cache design, RISC CPU architecture, and systems design.  As one of
the founders of MIPS Computer Systems, he played a key role in the
development of the MIPS architecture and the implementation of the
R20O0 RISC processor and associated systems.

Mark Horowitz is Associate Professor of Electrical Engineering at
Stanford University. His research interest is digital integrated
circuit design.  He has lead processor design projects at Stanford,
including MIPS-X, an early on-chip instruction cache, and TORCH, a
statically-scheduled superscaler processor.  He has also been part of
the DASH multiprocessor project that produced a 64-processor
shared-memory multiprocessor.

For information, call Dick Hester on 515-294-7686 or send e-mail to
hester@iastate.edu.

ISSCC93 Short Course Registration Fee: 
           $250 (Course materials and lunch included)

--
Koichi Yamashita (Fujitsu Laboratories Ltd.)
Assistant to Secretary, ISSCC93 Far East Program Committee
e-mail: yamashita@flab.fujitsu.co.jp