🚀 go-pugleaf

Hello,

We are responsible for the introductory VLSI design course here at Cornell, 
which results in submission to MOSIS of tinychip designs for fabrication 
under NSF sponsorship.

For several years, we ave succesfully used the design tools from Berkeley
(MAGIC, IRSIM, SPICE etc.). We have now acquired the GDT tools from 
Mentor Graphics, as several other universities and colleges. To use GDT
successfully, we will need:

On input:
	a. Incorporation of the MOSIS tchnology files into the GDT
	   application.
	b. Ability to translate standard cells, pads and the like
	   from CIF to the internal GDT format.
    
On output:
	a. Ability to translate designs done under GDT into CIF for
	   submission to MOSIS.

We have so far not located a College or University who has done this
routinely, so we are turning to the net for help. We would like to hear
from people who are doing this right now or have done it in the past.

a. Is it feasible? Are the tools/conversion programs available
b. How do the Mentor graphics tools compare with the Berkeley ones?


Thanks in advance,

christos
-- 
Christos Zoulas         | 389 Theory Center, Electrical Engineering,
christos@ee.cornell.edu | Cornell University, Ithaca NY 14853.
christos@crnlee.bitnet  | Phone: (607) 255 0302, Fax: (607) 255 9072