🚀 go-pugleaf

I am working on a CMOS-VLSI layout generator for digital circuits. 

For topological reasons I would like to limit the MINIMUM w/l
of a MOS transistor to 3 or 4 (in some physical design rules
of a process I have seen a minimal transistor width of 2).

Do you think, from your experience, this would have a strong
impact on the performance or the power consumption of a circuit?


----------------------------------------------------------------------
 Ronald Hindmarsh                      e-mail: ronald@cs.tu-berlin.de
 Institut fuer Technische Informatik
 TU Berlin FR 3-9
 Franklinstr. 29                            Phone: (+49) 30 314-73432
 W-1000 Berlin 10                             Fax: (+49) 30 314-21103
----------------------------------------------------------------------