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Article #693Re: Impact of minimal transistor width 3 or 4 instead of 2?
From: Paul Cohen
Date: Thu, 28 Jan 1993 02:23
Date: Thu, 28 Jan 1993 02:23
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1413 bytes
In article <1k1gi3INNbgs@news.cs.tu-berlin.de> ronald@cs.tu-berlin.de (Ronald Hindmarsh) writes: > >I am working on a CMOS-VLSI layout generator for digital circuits. > >For topological reasons I would like to limit the MINIMUM w/l >of a MOS transistor to 3 or 4 (in some physical design rules >of a process I have seen a minimal transistor width of 2). > >Do you think, from your experience, this would have a strong >impact on the performance or the power consumption of a circuit? > Depends mostly on the Delta W for the target process or processes. I've seen 2 micron processes with Delta W > 2, so if the transistor was drawn 2 microns wide, you'd have nothing left! Also, as W approaches Delta W, the characteristics really degrade. -- Paul B. Cohen | paul@aha.com Advanced Hardware Architectures, Inc. | paul@ic.berkeley.edu P.O Box 9669 | (208) 883-8000 (v) Moscow, ID 83843 | (208) 883-8001 (f)
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Path: arc1-ca.pugleaf.net!sparky!uunet!ukma!gatech!usenet.ins.cwru.edu!agate!canuck.Berkeley.EDU!paul From: paul@canuck.Berkeley.EDU (Paul Cohen) Newsgroups: comp.lsi Subject: Re: Impact of minimal transistor width 3 or 4 instead of 2? Date: 28 Jan 1993 02:23:37 GMT Organization: University of California at Berkeley Lines: 23 Message-ID: <1k7g39$hag@agate.berkeley.edu> References: <1k1gi3INNbgs@news.cs.tu-berlin.de> NNTP-Posting-Host: canuck.berkeley.edu Keywords: CMOS VLSI