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Archive-name: lsi-cad-faq/part2

    synthesis
  - De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings
    of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988

  SEHWA
  - University of Southern California, USA
  - pipeline-realizations from behavioral descriptions
  - Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE
    Design Automation Conference, pp. 454-460, IEEE 1986.

  SIEMENS' SYNTHESIS SYSTEM
  - Siemens, Germany
  - partitioning, data path allocation and scheduling
  - Scheichenzuber, J. et al.: "Global Hardware Synthesis from
    Behavioral Dataflow Descriptions", Proc. of the 27th DAC, pp. 456-461,
    June 1990.

  SOCRATES
  - General Electric, University of Colorado, USA
  - expert system
  - logic optimization and mapping for different technologies
  - de Geus, A.J., "The Socrates Logic Synthesis and Optimization System",
    Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers,
    1987.

  SPAID
  - Universty of Waterloo, Canada
  - DSP-synthesis for silicon compiler realizations
  - Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE
    Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989.

  SYNFUL
  - Bell-Northern Research, Canada
  - RTL and FSM synthesis for a production environment
  - G. Ward, "Logic Synthesis at BNR: A SYNFUL Story", Proceedings
    Canadian Conference on Very Large Scale Integration, October 1990.

  SYSTEM ARCHITECT'S WORKBENCH
  - Carnagie-Mellon University, USA
  - behavioral synthesis
  - Thomas, D. "The System Architect's Workbench", Proceedings of the 25th
    ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988

  UCB'S SYNTHESIS SYSTEM
  - UCB, USA
  - transformations, scheduling and data path allocation
  - Devadas, S.: "Algorithms for Hardware Allocation in Data Path
    Synthesis", IEEE Trans. on CAD, pp. 768-781, July 89

  SPLICER
  - University of Illinois, USA
  - scheduling and data-path allocation
  - Pangrle, B.M.: "Splicer: A Heuristic Approach to Connectivity
    Binding", Proc. of the 25th DAC, pp. 536-541, June 1988.

  V COMPILER
  - IBM, USA
  - scheduling and data path allocation from V-language
  - Berstis, V: "The V Compiler: Automatic Hardware Design", IEEE Design
    and Test, pp. 8-17, April 1989.

  VSS
  - Univ. of California at Irvine, USA
  - transformations, scheduling and data path allocation from VHDL to
    MILO
  - Lis, J. et al.: "Synthesis from VHDL", Proc. ICCD'88, pp. 378-381,
    October 1988.

  YORKTOWN SILICON COMPILER
  - IBM T.J.Watson Research Centre, USA
  - data path synthesis, logic synthesis etc.
  - Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation,
    pp. 204-311, Addison-Wesley, 1988

17: What free tools are there available, and what can they do?

  (This section can be viewed as a cross reference to the detailed descrip-
  tion of software that follows.)

    Analog VLSI and Neural Systems: Caltech VLSI CAD Tools

    Automated place and route: octtools, Lager

    Digital design environment: Galaxy CAD

    Lsi (polygon) schematic capture: magic, octtools(vem)

    Layout Verification: caltech tools (netcmp), gemini (Washington
    Univerity), wellchk (MUG)

    PCB auto/manual place and route: PADS pcb, PCB (Just for testing lsi
    designs, of course :)

    Simulation: irsim(comes with magic), esim, pspice, isplice3, watand,
    switcap2

    Synthesis: octtools, blis, Lager, item, (see section on synthesis)

    Standard schematic capture: PADS logic, PSPICE for windows

18: What Berkeley Tools are available for anonymous ftp?

  available from ic.berkeley.edu: (pub)

  adore: switched capacitor layout generator.  (Requires Octtools 5.1 to
  compile.)

  bdd:

  road: analog layout router

  sis: simplifies both sum-of-products and generic multi-level boolean
  expressions; it includes many tools including espresso, bdd

  ext2spice: enhanced ext2spice for use with magic

  available from gatekeeper.dec.com: (pub/misc)

  espresso: simplifies sum-of-products boolean expressions

19: What Berkeley Tools are available through ILP?

  (From MUG 20 Contributed by Carol Block of U. C. Berkeley)

  A new version of the popular circuit simulator, Spice3F2, is now avail-
  able from the Industrial Liaison Program (ILP) Office at the University
  of California, Berkeley.  A new release of Octtools will be forthcoming
  in 1993. Enclosed is a list of software distributed by this office.

  Adore, BBL.2, Berkeley Building-Block Layout System, Berkeley Computer
  Integrated Manufacturing System, Parameter Extraction Program for BSIM,
  Parameter Extraction for BSIM2, Bear-FP, Bert, BLIS, Spice 2G with BSIM
  Implementation, Cider, Ditroff/Gremlin, Ecstasy, EDIF 2 0 0, Elogic,
  ES1:Electrostatis 1-Dimensional Periodic Plasma, Franz Lisp, Gabriel,
  Glitter, IBC: Traveling-Wave-Tube Simulation, IEEE-754 Test Vector, Jsim,
  Jspice, Lanso, Magic-X11R3-Patch, Magic 1990 Decwrl/Livermore Release,
  Mahjong, Mighty, Octtools, Parmex Pix-Parmex, Plasma Device Simulation
  Codes, PLA Tools, Proteus, Ptolemy, Relax, Ritual, Sample, Sample-3D,
  Additional SAMPLE Documentation, Simpl-IPX and Simpl System 5, SIS, SPAM,
  Sparse, Spectre, Spice 2G6, Spice 3F2, Additional SPICE Documentation,
  Splat, Splice 3.0, Supercrystal, SWEC, Tempest, TimberWolf 3.2, Tsize,
  1986 VLSI Tools, Wombat.

  Within a few weeks, a new catalog will be available via anonymous FTP.
  Users will also be able to obtain forms, ordering instruc- tions and some
  software via this  means.   Generally,  recipients will  have  to com-
  plete an Agreement Form and pay a documentation and handling fee of about
  $250 per program.

  ILP can now distribute most of  its  programs  in  a  variety  of media,
  including: QIC-120, QIC-150, QIC-320, 8mm (2.2 gig), TK 50 (DEC tape for-
  mat), 9-track 1600 bpi and 9-track 6250  bpi.   Visa and  Mastercard ord-
  ers will be accepted on-line by 1993.  Most of the software may be freely
  redistributed either within an organi- zation  or  to other organiza-
  tions, both within the United States and abroad, subject to the certain
  restrictions,  including  all U.S.   Government restrictions, particu-
  larly those concerning ex- port.

          For additional information, contact:

               Industrial Liaison Program
               205 Cory Hall
               Software Distribution Office
               University of California at Berkeley
               Berkeley, CA  94720

               TEL: (510) 643-6687
               FAX: (510) 643-6694
               ilpsoftware@hera.berkeley.edu

20: Berkeley Spice (Current version 3f2)

  (From spice_info on ic.berkeley.edu)

    Acquiring Spice 3f2

  For more information on how to acquire Spice3f2, please send your physi-
  cal mailing address to "ilpsoftware@berkeley.edu" and request a software
  catalog.  This will give you all of the necessary information for order-
  ing Spice3f2 and other Berkeley CAD software, including an order form and
  use agreements.  At last check, the cost for spice3f2 was $250.00 (this
  price may change without notice).

    Systems supported and Formats Supplied

      Spice3f2 has been compiled on the following systems:
          Ultrix 4, RISC or VAX
          SunOS 4, Sun3 or Sun4
          AIX V3, RS/6000
          HP-UX 8.0, 9000/700
          MS-DOS on the IBM PC, using MicroSoft C 5.1 or later

  The following systems have been successfully tested either in the past or
  by someone outside of UC Berkeley.

          Dynix 3.0, Sequent Symmetry or Balance (does _not_ take advantage of
                  parallelism)
          HP-UX 7.0, 9000/300
          Irix 3.2, SGI Personal Iris
          NeXT 2.0
          Apple MacIntosh, Using Think C

  Spice3f2 is distributed in source form only.  The C compiler "gcc" has
  been used successfully to compile spice3f2, as well as the standard com-
  pilers for the systems listed above.

  Spice3 displays graphs under X11, PostScript, or a graphics-terminal
  independent library, or as a crude, spice2-like line-printer plot.  On
  the IBM PC, CGA, EGA, and VGA displays are supported through the Micro-
  Soft graphics library.  Note in particular that there is no Suntools
  interface.

  Note the the X11 interface to Spice3 expects realease 4 or later, and
  requires the "Athena Widgets Toolkit" ("Xaw") which may be available only
  in the "unsupported" portion of your vendor software.  A version of
  "OpenWindows" has problems due to undefined routines during linking --
  linking with a null copy of these routines has reportedly worked, but
  "OpenWindows" has not been tested in any way for this release.

  Note that for practical performance a math co-processor is required for
  an IBM PC based on the 286 processor.  A math co-processor is also recom-
  mended for the more advanced IBM PC systems.

  (from posting to comp.lsi.cad) The Windows NT port of spice3e2, Spice32,
  is available via ftp from site ftp.cica.indiana.edu, /pub/pc/win3/nt.
  Filename is spice100.zip. A similar port of nutmeg is included.

  The Unix distribution comes on 1/2" 9-track tape in "tar" format, TK50
  tape (DEC tape), or QIC-150 1/4" cartridge tape (Sun cartridge tape).
  The MS-DOS distribution comes on several 3.5" floppy diskettes (both high
  and low density) in the standard MS-DOS format.  The contents of both
  distributions are identical, including file names.

    New features in 3f2

  The following is a list of new features and fixes from the previous major
  release of Spice3 (3e.2) (see the user's manual for details):

                  AC and DC Sensitivity.
                  MOS3 discontinuity fix ("kappa").
                  Added a new JFET fitting parameter.
                  Minor initial conditions fix.
                  Rewritten or fixed "show" and "trace" commands.
                  New interactive commands "showmod" and "alter".
                  Minor bug-fixes to the Pole-Zero analysis.
                  Miscellaneous bug fixes in the front end.

              Additional features since release 3d.2 are:
                  Lossy transmission line model (not available under MS-DOS).
                  Proper calculation of sheet resistance in MOS models.
                  A new command ("where") to aid in debugging troublesome
                          circuits.
                  Smith-chart plots improved.
                  Arbitrary sources in subcircuits handled correctly.
                  Arbitrary source reciprocal calculations and DC biasing
                          now done correctly.
                  Minor bug-fixes to the Pole-Zero analysis.
                  Miscellaneous bug fixes in the front end.

    A Note on Version Numbering

  Spice versions are numbered "NXM", where "N" is a number representing the
  major release (as in re-write), "X" is a letter representing a feature
  change reflected by a change in the documentation, and "M" is a number
  indicating a minor revision or bug-patch number.

    FTP Access and Upgrades

  There is no anonymous ftp access for the Spice3 source.  The manual for
  spice3f2 (in it's postscript format) is available via anonymous ftp from
  "ic.berkeley.edu" in the directory "pub/spice3/um.3f.ps/".  If you are
  interested in the troff/me source, contact the email address below (the
  "make" files and whatnot are somewhat cumbersome for the manual).

  Patches or upgrades for Spice3 are _not_ normally supplied, however we
  have made exceptions to this rule, particularly in the case of minor ver-
  sion changes (such as 3f2 to 3f3).

    Email Address for Problems

  Please direct technical inquiries to "spice@berkeley.edu" or "spice-
  bugs@berkeley.edu" (for now these addresses are the same), and ordering
  or redistribution queries to "ilpsoftware@berkeley.edu".  If you find
  that your email to "spice" or "spice-bugs" doesn't get a response in a
  few days, resend your message.

21: Octtools (Current version 5.1)

  (From the ANNOUNCE-5.1 that comes with it)

  Octtools is a collection of programs and libraries that form an
  integrated system for IC design.  The system includes tools for PLA and
  multiple-level logic synthesis, state assignment, standard-cell, gate-
  matrix and macro-cell placement and routing, custom-cell design, circuit,
  switch and logic-level simulation, and a variety of utility programs for
  manipulating schematic, symbolic, and geometric design data.  Most tools
  are integrated with the Oct data manager and the VEM user interface.

  The software requires UNIX, the window system X11R4 including the Athena
  Widget Set. The design manager VOV and a few other tools require the C++
  compiler g++.

  Octtools-5.1 have been built and tested on the following combinations of
  machines and operating systems: DECstation 3100, 5000 running Ultrix 4.1
  and 4.2; DEC VAX running Ultrix 4.1 and 4.2; Sun 3 and 4 running OS 4.0
  and Sun SparcStation running OS 4.0.  The program has been tried on the
  following machines, but is not supported: Sequent Symmetry, IBM RS/6000
  running AIX 3.1.

  To obtain a copy of Octtools 5.1 (8mm, tk50, or 1/4inch cartridge QIC150)
  and a printed copy of the documentation) for a $250 distribution charge,
  see section on Berkeley ILP.

  Questions may be directed to octtools@ic.berkeley.edu.

22: Ptolemy (Current version 0.4):

  (From comp.dsp FAQ)

  Ptolemy provides a highly flexible foundation for the specification,
  simulation, and rapid prototyping of systems.  It is an object oriented
  framework within which diverse models of computation can co-exist and
  interact.  For example, using Ptolemy a data-flow system can be easily
  connected to a hardware simulator which in turn may be connected to a
  discrete-event system, etc.  Because of this, Ptolemy can be used to
  model entire systems.

  In addition, Ptolemy now has code generation capabilities.  From a flow
  graph description, Ptolemy can generate both C code and DSP assembly code
  for rapid prototyping.  Note that code generation is not yet complete,
  and is included in the current release for demonstration purposes only.

  Ptolemy has been used for a broad range of applications including signal
  processing, telecomunications, parallel processing, wireless communica-
  tions, optical phase lock loops, real time systems, and hardware/software
  co-design.  Ptolemy has also been used as a lab for signal processing and
  communications courses.  Currently Ptolemy has hundreds of users in over
  75 sites, both in industry and academia.

  Ptolemy is available for the Sun 4 (sparc) and DecStation (MIPS) archi-
  tectures.  A port to the HP workstation is in progress.  Installing the
  system requires 49 Mbytes for Ptolemy (64 Mbytes after you optionally
  rebuild) and 16 Mbytes for the Gnu tools subset.  At least 8 Mbytes of
  physical memory are required.

  Ptolemy has been developed at UC Berkeley over the past 3 years.  Further
  information, including papers and the complete release notes, is avail-
  able from the FTP site.

  A license is no longer required to receive Ptolemy.  The source code,
  binaries, and documentation are available by anonymous ftp from
  ptolemy.berkeley.edu, under /pub/ptolemy. Consult the file /pub/README
  for further information.

23: Lager (Current version 4.0):

  (From MUG 18)

  The LAGER system is a set of CAD tools for performing parameterized VLSI
  design with a slant towards DSP applications (but not limited to DSP
  applications).  A standard cell library, datapath library, several module
  generators and several pad libraries comprise the cell library.  These
  tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
  sippi State, and ITD.  The tool development has been funded by DARPA
  under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
  ley).  LAGER 3.0 was described in MUG 15.

  Send email to reese@erc.msstate.edu if you are interested in obtaining
  the toolset via FTP. If you cannot get the distribution via ftp then send
  one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
  by phone at (601)-325-3670 or at one of the following addresses:

          (US Mail Address)
          P.O. Box 6176
          Mississippi State, MS 39762

          (FEDEX)
          2 Research Boulevard
          Starkville, MS 39759

  Be sure to include a return FEDEX waybill we can use to ship your tape
  back to you. Instead of sending a tape and FEDX waybill, you can also
  just send us a check for $75 and we will send you back a tape.  Make the
  check payable to Mississippi State Univ.  The tape will be written on a
  high density tape drive (150 Mb).  Older low density SUN tape drives (60
  Mb) cannot read this format so you need to have access to one of SUN's
  newer tape drives.

24: BLIS (Current version 2.0):

  (From their announcement posted here)

  BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
  synthesis of digital circuits from high-level descriptions.  Version 2.0
  supports functional-level synthesis starting from the ELLA hardware
  description language.  Other languages can easily be supported by inter-
  facing a parser to the internal data-flow representation of BLIS.

  BLIS is distributed through the Industrial Liason's Program (ILP) Office
  of the UCB EECS department.  The cost of $250 covers media and distribu-
  tion charges.  Binaries are provided for SUN4 and DEC MIPS architectures
  but BLIS should compile on most other machines supported by the GNU C and
  C++ compilers (e.g. HP, vax, etc).  ELLA language documentation and simu-
  lator are not supplied with the BLIS distribution, but can be obtained
  from Computer General.

25: COSMOS and BDD

  (From their announcement posted here)

                Obtaining and installing COSMOS and BDD.

  The COSMOS package generates switch-level simulators for MOS circuits.
  The BDD package is a subset of COSMOS providing a set of library routines
  for symbolic Boolean manipulation.

  To obtain a copy of either COSMOS or BDD via FTP:

  1. Create an appropriate subdirectory.  For COSMOS, you may want to
     create a symbolic link /usr/cosmos to this directory, although this is
     not essential.

  2. Connect to the subdirectory

  3. FTP to n3.sp.cs.cmu.edu (login anonymous, password
     yourname@your.host.name)

  4. Type:

             cd /usr/cosmos/ftp
             ls

  5. Select which version of the code you want.  The files are named
     bdd.XXX.YYY.tar.Z and cosmos.XXX.YYY.tar.Z, where XXX.YYY is the ver-
     sion number.  Generally you should select the highest numbered ver-
     sion.

  6. 6. Type:
             get <FILE> (where <FILE> is the file name of the selected ver-
     sion).
             get README
             quit

  7. Follow the instructions in README

  8. Send the following information to cosmos@cs.cmu.edu

             Your name
             Your postal address
             Your net address
             The file retrieved
             The date of your retrieval

  COSMOS and BDD are made available with the understanding that no part of
  it will be redistributed further without permission.

  Last updated 18 July 1991 by Derek Beatty.

  26: ITEM

  (Taken from the item.news file contained in the package:)

  The first public release of ITEM, UCSC's logic minimizer using if-then-
  else DAGs, was made 2 January 1991.  The system is available by anonymous
  ftp from ftp.cse.ucsc.edu, in directory pub/item as a compressed tar
  archive (item.tar.Z).  Also available are tech reports about the algo-
  rithms and data structures (88-28, 88-29, and 90-43).

  ITEM can also be found at ftp.cse.ucsc.edu in the pub/item directory.

27: PADS logic/PADS PCB:

  While this is a commercial product, they have just recently made avail-
  able a shareware version.  This version is fully functional and indenti-
  cal to their schematic capture and PCB autoplace and route software
  except that it is limited to about 50 components.  It is available for
  IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at
  several sites including wuarchive.wustl.edu in
  /mirrors/msdos/cad/pads*.zip.  There is a $50 registration fee if you
  would like to get future updates from them.

28: Another PCB Layout Package:

  (from Randy Nevin <randyn@microsoft.com>:)

  I'm distributing a freely-copyable software package to do autorouting of
  (1- and 2-layer) printed circuit boards on a PC or compatible. It is
  written in C (with a little .asm), and all source code is included. There
  is an autorouter, a board viewer, a rat nest viewer, and some output
  filters which generate postscript and hp laserjet output files. There is
  no charge, but I maintain the copyright (it is not public domain). If you
  want to read about it, I published an article on autorouting algorithms
  in the sept '89 dr. dobb's journal. ega is required (for the viewing pro-
  grams). If you'd like to get the software, send me a stamped, self-
  addressed floppy mailer and a floppy. I can handle 5.25" 360K or 1.2M, or
  3.5" 1.4M, but if you send 360K there is some extra code that I won't be
  able to fit on the disk, so high density is better.

  I developed this software at home on my own time, and it is not related
  to what I do for my employer, so I will not use my employer's email
  resource to distribute it. however, it is available for anonymous ftp
  access on wsmr-simtel20.army.mil in PD1:<MSDOS.CAD>PCB.ARC, last I heard.
  I do not keep simtel up to date. But the version there is useable, and
  does include all source code.

          Randy Nevin
          24135 SE 16th PL
          Issaquah, WA 98027

29: Magic (Current version 6.3):

  This is a polygon based lsi layout editor.  It is capable of reading and
  writing magic, calma (version 3.0, corresponding to GDS II Release 5.1),
  and cif.  It is available for anonymous ftp from gatekeeper.dec.com in
  /pub/DEC/magic.

30: PSpice:

  This is a commercial product, however, they do have a student version
  that is available (limited to around 16 transistors).

          PC dos version: 5.0 wuarchive.wustl.edu in
                          /mirrors/msdos/electrical/,
                          pspice5a.zip, pspice5b.zip, pspice5c.zip

          PC windows3 version 5.1: WSMR-SIMTEL20.Army.Mil in
                          pd1:<msdos.windows3>
                          called PSPIC51A.ZIP and PSPIC51B.ZIP

          Mac version 5.1: wuarchive.wustl.edu in
                          /mirrors/info-mac/app/pspice-51.hqx

  The PC version is also available at a number of U.S. and non-U.S. sites.

31: Esim:

  A new version of the switch-level simulator ESIM that can handle CMOS
  transmission gates is available through MUG, ftp venera.isi.edu
  (128.9.0.32))

32: Isplice3 (Current version 2.0):

  This is a high level simulator, I do not know much more then that.  It is
  available via anonymous ftp from uicadb.csl.uiuc.edu.

33: Watand:

  (From Phil Munro's posting <FC138001@ysub.ysu.edu>)

  Spice is not the only circuit simulator available.  There is one called
  WATAND (WATerloo ANalysis and Design) which runs on a mainframe (and some
  other workstations).  We use it here under CMS on our mainframe computer.

  Unlike Spice and its derivatives, Watand is a fully *interactive* pro-
  gram; that is, one enters an environment where analyses can be run and
  rerun, values changed and queried, options changed, and even different
  circuits can be run, all without leaving the environment.

     "WATAND Users Manual", by Dr. Phil Munro, April 1992, 233 pages,
     unbound, $7.00 plus whatever shipping charges the bookstore might ask
     of you.

     "WATAND Introduction and Examples", by Dr. P. Munro, September 1991,
     160 pages, spiral bound, incomplete edition Chapters 1 - 10.  The cost
     is $4 or $5, I think, plus shipping.

               You should write to Youngstown State University Bookstore
                               Youngstown, Ohio 44555

  Watand itself is available from Mark O'Leavey, Waterloo Engineering
  Software, 22 King St. S., Suite 302, Waterloo, Ontario, CANADA, N2L 1C6.
  Fax: (519) 746-7931 Phone: (519) 741-8097. It's currently only available
  for DECStation and Sparcstation.

34: Caltech VLSI CAD Tools:

  (From John Lazzaro <lazzaro@boom.CS.Berkeley.EDU>)

                     Caltech VLSI CAD Tool Distribution

  We are offering to the Internet community a pre-release version of the
  Caltech electronic CAD system for analog VLSI neural networks.  This dis-
  tribution contains tools for schematic capture, netlist creation, and
  analog and digital simulation (log), IC mask layout, extraction, and DRC
  (wol), simple chip compilation (wolcomp), MOSIS fabrication request gen-
  eration (mosis), netlist comparison (netcmp), data plotting (view) and
  postscript graphics editing (until). These tools were used exclusively
  for the design and test of all the integrated circuits described in
  Carver Mead's book "Analog VLSI and Neural Systems".  Until was used as
  the primary tool for figure creation for the book.  The distribution also
  contains an example of an analog VLSI chip that was designed and fabri-
  cated with these tools, and an example of an Actel field-programmable
  gate array design that was simulated and converted to Actel format with
  these tools.

  These tools are distributed under a license very similar to the GNU
  license; the minor changes protect Caltech from liability.

  To use these tools, you need:

  1) A unix workstation that runs X11r3, X11r4, or Openwindows

  2) A color screen

  3) Gcc or other ANSI-standard compiler

  Right now only Sun Sparcstations are officially supported, although
  resourceful users have the tools running on Sun 3, HP Series 300, and
  Decstations.  If don't have a Sparcstation or an HP 300, only take the
  package if you feel confident in your C/Unix abilities to do the porting
  required; someday soon we will integrate the changes back into the
  sources officially, although many "ifdef mips" are already in the code.

  If you are interested in some or all of these tools,

  1) ftp to hobiecat.cs.caltech.edu on the Internet,

  2) log in as anonymous and use your username as the password

  3) cd ~ftp/pub/chipmunk

  4) copy the file README, that contains more information.

  European researchers can access these files through anonymous ftp using
  the machine ifi.uio.no in Norway; the files are in the directory chip-
  munk.  We are unable to help users who do not have Internet ftp access.

35: Switcap2 (Current version 1.1):

  This is a switched capactor simulator.  It is available from:

                  SWITCAP Distribution centre,
                  411 Low Memorial Library,
                  New York,
                  N.Y. 10027.

36: Test Software for Abramovici Text:

  (Contributed by Mel Breuer of the Univ. of Southern California)

  Many faculty are using the text by Abramovici, Breuer, and Fried- man
  entitled  "Digital Systems Testing and Testable Design" in a class on
  testing.  They have expressed an interest to  supplement their  course
  with software tools.  At USC we have developed such a suite of tools.
  They include a  good  value  simulator,  fault simulator,  fault  col-
  lapsing  module, and D-algorithm-based ATPG module for combinational
  logic.  The software has  been  specifi- cally  designed  to  be easily
  understood, modified and enhanced.  The algorithms follow those described
  in the text.  The  software can  be  run  in many modes, such as one
  module at a time, single step, interactively or as a batch process.  Stu-
  dents can use  the software  "as  is"  to  study  the operation of the
  various algo- rithms, e.g. simulation of a latch using different delay
  models.  Also,  simple  programming  projects can be given, such as
  extend the simulator from a 3-valued system to  a  5-valued  system;  or
  change  the D-algorithm so that it only does single path sensiti- zation.
  There  are  literally  over  50  interesting   software enhancements
  that  can  be made by changing only a small part of the code.  The system
  is written in C and runs on a SUN.

  If you are currently using the Abramovici text and would  like  a copy
  of  this  software,  please  send a message to Prof. Melvin Breuer at
  mb@poisson.usc.edu.

37: Test Generation and Fault Simulation Software

  (Contributed by Dr. Dong Ha of Virginia Tech)

  Two automatic test pattern generators (ATPGs) and a fault simula- tor
  for  combinational circuits were developed at Virginia Tech, and the
  source codes of  the  tools  are  now  ready  for  public release.
  ATLANTA is an ATPG for stuck-at faults.  It is based on the FAN algorithm
  and a parallel-pattern,  single-fault  propaga- tion  technique.   It
  consists of optional sessions using random pattern testing, deterministic
  test pattern generation  and  test compaction.  SOPRANO is an ATPG for
  stuck-open faults.  The algo- rithm of SOPRANO is similar to  ATLANTA
  except  two  consecutive patterns  are  applied  to  detect a stuck-open
  fault.  FSIM is a parallel-pattern, single-fault  simulator.   All  the
  tools  are written  in  C.  The source codes are fully commented, and
  README files contain user's manuals.  Technical papers about  the  tools
  were  presented at DAC-90 and ITC-91. All three tools are free to univer-
  sities.  Companies are requested to make a contribution  of $5000  but
  will have free technical assistance.  For detailed in- formation, con-
  tact:

             Dr. Dong Ha
             Electrical Engineering
             Virginia Tech
             Blacksburg, VA 24061
             TEL: 703-231-4942
             FAX: 703-231-3362
             dsha@vtvm1.cc.vt.edu

38: Olympus Synthesis System

  (From Rajesh K. Gupta <rgupta@sirius.Stanford.EDU>)

  Recently there have been several enquiries about the Olympus Synthesis
  System. Here are answers to some commonly asked questions. For details
  please send mail to "synthesis@chronos.stanford.edu".

  1. What is Olympus Synthesis System?

  Olympus is a result of a continuing project on synthesis of digital cir-
  cuits here at Stanford University. Currently, Olympus synthesis system
  consists of a set of programs that perform synthesis tasks for synchro-
  nous, non-pipelined circuits starting from a description in a hardware
  description language, HardwareC.

  The output of synthesis is a technology independent netlist of gates.
  This netlist can be input to logic synthesis and technology mapping tools
  within Olympus or to UC Berkeley's mis/sis. Current technology mapping in
  Olympus is targeted for LSI logic standard cells and a set of PGA archi-
  tectures: Actel and Xilinx.

  2. How is Olympus distributed?

  The source code and documentation for Olympus is distributed via ftp.

  3. What are the system requirements for Olympus?

  Olympus has been tested on following hardware platforms: mips, sparc,
  hp9000s300, hp9000s800, hp9000s700, vax.  All the programs in Olympus
  come with a default menu-driven ASCII interface. There is also a graphi-
  cal user interface, called "olympus", provided with the distribution.
  This interface is written using Motif procedures.

  You would need about 40 MBytes of disk space to extract and compile the
  system.

  4. How can I obtain a copy of Olympus?

  Olympus is distributed free of charge by Stanford University.  However,
  it is not available via anonymous ftp. In order to obtain a copy please
  send a mail to "olympus@chronos.stanford.edu" where an automatic-reply
  mailer would send instructions for obtaining Olympus software.

39: OASIS logic synthesis

  (From William R. Richards Jr. <richards@mcnc.org>)

  OASIS is a complete logic synthesis system based on the Logic3 HDL
  develped at MCNC (unfortunately neither VHDL or Verilog compatible).
  kk@mcnc.org is the person responsible for it. OASIS is available to US
  universities for $500 and non-US universities for $600. Industrial
  license is $3000.

40: CAzM, a Spice-like table-based analog circuit simulator

  (From William R. Richards Jr. <richards@mcnc.org>)

  Second is CAzM, a Spice-like table-based analog circuit simulator. It
  offers significant performance advantages over other Berkeley Spice
  derivatives. It is used fairly extensively in our design community.  US
  university license is $175, non-US $250. Commercial license is $800. It
  comes with an X11- based signal viewing tool Sigview which is public
  domain and may be anonymous ftp'd from mcnc.org. I am the primary contact
  for CAzM at MCNC.

41: Galaxy CAD, integrated environment for digital design for Macintosh

  Thanks to Simon Leung <sleung@sun1.atitech.ca>

  The Galaxy CAD System is an integrated environment for digital design and
  for rapid prototyping of CAD tools and other software.  The system
  currently includes schematic capture and simulation of both low-level and
  high-level digital designs and is being expanded to include physical
  design tools.  Galaxy runs on a number of 680X0 platforms, including the
  Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST.  Others will be
  added according to demand.

  The Galaxy CAD System is an ideal environment for teaching digital
  design.  It has been used successfully for both introductory logic design
  and computer design courses at Wisconsin.  Some of the features of Galaxy
  that make it suitable for education are:

  1.  Integrated multiple-window environment: All Galaxy tools run
      concurrently in a multiple window environment.  Copying data
      from one window to another is simple.  Any number of simulation
      sessions can be active simultaneously.

  2.  Hierarchy: the schematic editor and simulator are both fully
      hierarchical.  Building hierarchical designs is simple, including
      creating symbols for modules.  The simulator is a true hierarchical
      simulator: it does not require a time-consuming macro-expansion
      step.

  3.  Integrated editing and simulation: Designs are edited and
      simulated in the same environment.  Simulation input and output
      can be shown directly on schematics, allowing direct manipulation
      of net values.  Unlike other products, Galaxy does not require
      modification of the schematic to insert "switch" and "light"
      components.  In addition, Galaxy allows display of bus values in
      hexadecimal directly on schematics to simplify debugging of
      high-level designs.  Simulation I/O can also use waveforms,
      text files, and tables.

  4.  Faults: Stuck-at faults can be introduced on the schematic
      editor and simulated immediately without rebuilding the
      simulation model.  This provides an excellent way to display
      the effects of faults.

  5.  Buses: Galaxy supports specification and simulation of bus
      structures, including complex extractions, fanouts, and bit
      reversal.  Buses are specified by annotating nets with text.
      For simulation, buses are kept intact so that multiple-bit
      high-level components can be used.  Galaxy includes a library
      of register-transfer components suitable for high-level
      computer design and simulation.

  6.  Alternate specification of designs: In addition to schematics,
      Galaxy users can specify design modules using a textual HDL
      (GHDL) and using hardware flowcharts and state diagrams.  A
      hierarchical design can mix these representations as desired.

  7.  High-quality PostScript output: Galaxy schematics are of excellent
      quality.  Gates are drawn according to standard practices, e.g.,
      OR gates are drawn with the correct circular arcs and not ellipses.

  8.  Uniform user interface: Galaxy tools have the same user interface
      on all platforms, reducing student learning curves.  In fact,
      the same tool OBJECT CODE runs on all platforms due to the unique
      structure of Galaxy.

  9.  Adding new simulation primitives is straightforward.

  10. No cost: Galaxy is available for free via anonymous FTP (Apple
      Macintosh version).  Other versions will be made available based
      on demand.

  Galaxy is also an excellent environment for rapid prototyping of new CAD
  tools.  By building on top of available resources, we have been able to
  prototype new tools in days or weeks that would ordinarily have taken
  months or years.  For more information, send e-mail.

  To obtain Galaxy CAD, connect to "eceserv0.ece.wisc.edu" using FTP.  Log
  in as "anonymous" with password "guest".  Galaxy is in directory
  "pub/galaxy".  The file "README" in that directory gives further instruc-
  tions.  Please register as a user by sending e-mail to
  "beetem@engr.wisc.edu".

  John F. Beetem
  ECE Department
  University of Wisconsin - Madison
  Madison, WI  53706
  USA
  (608) 262-6229
  beetem@engr.wisc.edu

42: Gabriel DSP development system

  The Gabriel software is available via ftp from copernicus.Berkeley.EDU
  (128.32.240.37).  It's not quite "anonymous": you can use anonymous ftp
  to get the license agreement.  When you sign that and mail it back to us,
  we give you the password to an ftp account that allows you to grab the
  actual software.  It's free, just not anonymous.  :-)

  For the uninitiated, Gabriel is a block diagram programming environment
  for DSP that runs on Sun 3 and Sun 4 workstations.  It can simulate DSP
  designs, generate assembly code for Motorola DSP56000 and DSP96000 chips,
  and automatically perform parallel scheduling when multiple DSP chips are
  used.

  For more information, ftp to copernicus.Berkeley.EDU, log in as
  "anonymous" (any password will do), and grab the files "gabriel-
  overview", "gabriel-release-info", and "gabriel-license.shar".  Be warned
  that a new version of Gabriel will be out by the end of January, so if
  you're interested in it, it might pay to wait until then.

  Phil Lapsley
  phil@ucbarpa.Berkeley.EDU

43: WireC graphical/procedural system for schematic information

  (From Larry McMurchie <larry@cs.washington.edu>)

  WireC is a graphical specification language that combines schematics with
  procedural constructs for describing complex microelectronic systems.
  WireC allows the designer to choose the appropriate representation,
  either graphical or procedural, at a fine-grain level depending on the
  characteristics of the circuit being designed.  Drawing traditional
  schematic symbols and their interconnections provides fast intuitive
  interaction with a circuit design while procedural constructs give the
  power and flexibility to describe circuit structures algorithmically and
  allow single descriptions to represent whole families of devices.

  The procedural capability of WireC allows other CAD tools to be incor-
  porated into the design system.  For example, we have defined an inter-
  face to the SIS logic synthesis system wherein the designer can represent
  part of the system behaviorally.  WireC invokes logic synthesis on these
  components to produce a structural description that can be incorporated
  into the rest of the design.

  Libraries of devices defining a particular netlist output format may be
  defined by the user. The libraries currently distributed with WireC
  include a default CMOS gate library whose output is the SIM format.  This
  format can be simulated with COSMOS or IRSIM and compared against a cir-
  cuit extracted from layout.  This library also includes devices that
  allow a behavioral description to be synthesized and mapped using MIS or
  SIS and incorporated into a larger circuit.

  Another library is the xnf library for designing systems with Xilinx
  FPGAs.  Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC,
  this library contains devices specific to the 2000 and 3000 series Xilinx
  LCA's.  In addition to drawing the devices explicitly, one can represent
  parts of a circuit with equations and have these synthesized automati-
  cally.

  Currently in progress is a library of CMOS gates for Cascade Design
  Automation's ChipCrafter product.  WireC provides a mixed
  schematic/procedural design frontend for ChipCrafter, which uses module
  generation, timing analysis and place and route software to create a phy-
  sical layout from the WireC design specification.

  WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed
  Tellman.  We are interested in any libraries you may develop and will
  provide a limited degree of support.

  WireC requires an X-Windows compatible environment and a C++ compiler
  such as Gnu G++ and AT&T CC.  WireC is available via ftp on the Internet.
  For details send mail to

  larry@cs.washington.edu ebeling@cs.washington.edu

44: LateX circuit symbols for schematic generation

  (From Adrian Johnstone <adrian@cs.rhbnc.ac.uk)

  A set of circuit schematic symbols are available for use in LaTeX picture
  mode. The set includes all basic logic gates in four orientations, FETs,
  power supply pins, transmission gates, capacitors, resistors and wiring
  T-junctions. All pins are on a 1mm grid and the symbols are designed to
  be easily used with Georg Horn's TeXcad program: we even supply you with
  a palette picture file that displays all 52 symbols in a compact grid
  that you can cut and paste from within TeXcad. Each symbol lives in its
  own .mac file and is defined as a 'savebox' so as to reduce memory con-
  sumption. You must add the [bezier] option to your 'documentstyle' com-
  mand. A small manual is provided in both Postscript and .dvi forms.

  The files lcircuit.zip and lcircuit.tar are available for anonymous ftp
  from cscx.cs.rhbnc.ac.uk (134.219.200.45) in directory pub/lcircuit. I
  will also be uploading them to various ftp servers in the coming week.

45: Tanner Research Tools (Ledit and LVS)

  (From Bhusan Gupta <bgupta@micro.caltech.edu>)

  There is a "low" cost tool from Tanner Research (Pasadena, Ca) called LVS
  that will compare two spice decks.  It is a tool that is still evolving
  and is flexible. It can be a lifesaver if you have to compare spice
  decks. It is much easier to use than netcmp/netcomp (the caltech VLSI
  tools). I realize that this is a commercial tool for $, but the only rea-
  son I suggest it is that it isn't as expensive as a tool from a main-line
  CAD vendor.  (University pricing is around $245 for the PC version, and
  $995 for the commercial version.)

  Tanner also sells a layout mask editor called Ledit which they sell for
  the PC, Sun, HP, and Mac platforms. It has a DRC tool, extract to spice,
  a cross-section viewer, etc for additional money.  The cross-section
  viewer is neat gadget in that given some of your design, it will show
  what the vertical cross-section looks like.  Demo versions are available.

  For more info contact Tanner Research - 180 N. Vinedo Ave. Pasadena 91107
  (818) 792-3000 or fax (818) 792-0300.