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Article #699Re: Impact of minimal transistor width 3 or 4 instead of 2?
From: Brian A. Blow
Date: Tue, 26 Jan 1993 14:33
Date: Tue, 26 Jan 1993 14:33
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Ronald Hindmarsh (ronald@cs.tu-berlin.de) wrote: : I am working on a CMOS-VLSI layout generator for digital circuits. : For topological reasons I would like to limit the MINIMUM w/l : of a MOS transistor to 3 or 4 (in some physical design rules : of a process I have seen a minimal transistor width of 2). : Do you think, from your experience, this would have a strong : impact on the performance or the power consumption of a circuit? Using wider transistors will mean that you will have to drive larger gate capacitances. This will lead to a slightly increased power consumption. If you use wider transistors to drive these gates, you will have a greater charging/discharging current to do this, so circuit speed should not significantly change. Brian Blow brian.blow@medtronic.com Medtronic, Inc. (612) 574-4030 Minneapolis, MN
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Newsgroups: comp.lsi Path: arc1-ca.pugleaf.net!sparky!uunet!rosevax!medtron!bb11807 From: bb11807@medtronic.COM (Brian A. Blow) Subject: Re: Impact of minimal transistor width 3 or 4 instead of 2? Message-ID: <1993Jan26.143317.6395@medtron.medtronic.com> Sender: news@medtron.medtronic.com (USENET News Administration) Nntp-Posting-Host: thug.pace.medtronic.com Organization: Medtronic, Inc. X-Newsreader: TIN [version 1.1 PL8] References: <1k1gi3INNbgs@news.cs.tu-berlin.de> Date: Tue, 26 Jan 1993 14:33:17 GMT Lines: 22