Article View: comp.lsi
Article #706CFP: Special Issue on FPGAs
From: Dinesh Bhatia
Date: Fri, 08 Jan 1993 22:29
Date: Fri, 08 Jan 1993 22:29
67 lines
2729 bytes
2729 bytes
CALL FOR PAPERS
VLSI DESIGN
An International Journal of Custom-Chip Design, Simulation, and Testing
Special Issue
on
Field-Programmable Gate Arrays (FPGAs)
Field-Programmable Gate Arrays (FPGAs) have emerged as a revolutionary technology
for very rapid prototyping. FPGA based systems allow total configurability and have
achieved performance close to that of supercomputers. Real time hardware emulation
is very easily accomplished using FPGAs.
This special issue will explore innovative
ways for enhancing FPGA architecture, CAD for FPGAs, and FPGA applications.
Original contributions are sought in all areas related to FPGAs. Specific topics of
interest include, but are not limited to:
o FPGA Architecture
Logic Block and Routing Architecture, New Innovative Designs.
o CAD for FPGAs
Logic Synthesis, Partitioning, Placement and Routing, Testing.
o FPGA Applications
Rapid Prototyping, Hardware Emulators, Accelerators.
o Fabrication Technology
Programming Technology.
Prospective authors are invited to submit five copies of complete manuscript of high
quality research contributions by May 31, 1993 to the Guest Editor:
Dr. Dinesh Bhatia, Guest Editor
ECE Department, ML 0030
University of Cincinnati
Cincinnati, OH 45221-0030
Phone: 513-556-2570
E-mail: Dinesh.Bhatia@UC.EDU
Instructions for Manuscript Preparation:
Papers should not exceed 30 double spaced pages. This includes figures and
tables if any. Paers should not have been previously published. Also we cannot accept
papers that have been submitted elsewhere for publication. Papers should include
a clear title, author(s), address(es), telephone number(s), and FAX number(s). A
clear abstract not to exceed 300 words and a list of key words is also required. A
publication history for paper is also required for previously published abstracts
and conference notes.
FOR FURTHER DETAILS PLEASE CONTACT DR. DINESH BHATIA
PUBLISHER:
Gordon and Breach Science Publishers
Technical Details
Message-ID:
<C0K3t4.HH5@babbage.ece.uc.edu>Path:
arc1-ca.pugleaf.net!sparky!uunet!gatech!darwin.sura.net!zaphod.mps.ohio-state.edu!malgudi.oar.net!caen!news.cs.indiana.edu!babbage.ece.uc.edu!surya.ece.uc.edu!dineshShow Full Headers
Complete Article Headers
Newsgroups: comp.lsi Path: arc1-ca.pugleaf.net!sparky!uunet!gatech!darwin.sura.net!zaphod.mps.ohio-state.edu!malgudi.oar.net!caen!news.cs.indiana.edu!babbage.ece.uc.edu!surya.ece.uc.edu!dinesh From: dinesh@surya.ece.uc.edu (Dinesh Bhatia) Subject: CFP: Special Issue on FPGAs Message-ID: <C0K3t4.HH5@babbage.ece.uc.edu> Keywords: FPGAs Sender: root@babbage.ece.uc.edu (Operator) Nntp-Posting-Host: surya.ece.uc.edu Organization: University of Cincinnati Date: Fri, 8 Jan 1993 22:29:27 GMT Lines: 68