Register file design

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Article #811

#811

From: marc
Date: Mon, 18 May 1987 17:32

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	I am currently designing the datapath of a processor. We
	are implementing some fault-tolerance techniques in the
	design, more specifically around the register file.

	I would like to know if there is any register file design
	available in the following format:
		"MOSIS Scalable CMOS technology"
	
	I am looking for layouts of the following cells:
		- basic register cell (preferably STATIC)
		- register address decoder
		- precharge circuitry
		- sense amplifier

	Thank you for your help,
					Marc Tremblay
					marc@CS.UCLA.EDU

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Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!rutgers!mit-eddie!genrad!decvax!ucbvax!CS.UCLA.EDU!marc
From: marc@CS.UCLA.EDU
Newsgroups: comp.lsi
Subject: Register file design
Message-ID: <8705181732.AA14166@zeus.CS.UCLA.EDU>
Date: Mon, 18-May-87 13:32:24 EDT
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Posted: Mon May 18 13:32:24 1987
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