Article View: comp.lsi
Article #925Re: Content Addressable Memory
From: Mark G. Johnson
Date: Mon, 16 Nov 1987 16:56
Date: Mon, 16 Nov 1987 16:56
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2692 bytes
In article <5307@cisunx.UUCP>,
adbst@unix.cis.pittsburgh.edu.UUCP (Andrew D. Bowen) writes
> I am working on a Content Addressable Memory Chip... So far, all
> other designs that I have come across have used a static cell.
> My design is dynamic. Does anyone know of anyone else who is
> designing a dynamic CAM cell. I have built up from a 4-fet design
> using all N-Channels. So far, spice have been giving me favorable
> results. Does anyone know why dynamic cells are not built?
> Andy Bowen
Workers at General Electric have a patent (US #3,701,980) on a 4
transistor dynamic CAM cell. It's also described in the IEEE Journal
of Solid-State Circuits, October 1972, p. 364 (Mundy et al., vol SC-7).
Most people add a fifth transistor to this cell, to increase margins
and decrease power during a match. The 5T cell (in spice format) is
M1 10 50 70 Vbb Nch w=? l=?
M2 20 50 80 Vbb Nch w=? l=?
M3 10 70 90 Vbb Nch w=? l=?
M4 20 80 90 Vbb Nch w=? l=?
M5 100 100 90 Vbb Nch w=? l=?
where (10 and 20) are the bitlines, (50) is the write (word) line, and
(100) is the match line. To get the 4-transistor version, delete M5
and hook up the match line to node 90.
MIT has a "Smart Memory Project" underway; they are using a 5T dynamic
CAM cell to build a "Database Accelerator" chip and board. They've
published their cell design (which is the above except that the gate
nodes of M3 and M4 are swapped) in the 1985 IEDM (Wade and Sodini).
One feature of Wade's cell is that it stores four states; as I recall,
they are 0, 1, Always_Match, and Dont_Care. This allows some fairly
powerful logic-in-memory operations. Somewhere, can't remember the
reference, they published an extensive paper on the architecture,
applications, and software for the Database Accelerator. The author
was Richard Zippel.
Wade also has a 3-transistor dynamic CAM cell which uses both PMOS
and NMOS transistors. You might give Jon Wade at MIT a call; he is
(was?) finishing up his Ph.D. on the Database Accelerator.
--
-Mark Johnson *** DISCLAIMER: The opinions above are personal. ***
UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark TEL: 408-720-1700 x208
US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!mark From: mark@mips.UUCP (Mark G. Johnson) Newsgroups: comp.lsi,comp.arch Subject: Re: Content Addressable Memory Message-ID: <912@obiwan.UUCP> Date: Mon, 16-Nov-87 11:56:34 EST Article-I.D.: obiwan.912 Posted: Mon Nov 16 11:56:34 1987 Date-Received: Wed, 18-Nov-87 04:41:25 EST Lines: 44