Article View: comp.lsi
Article #945Re: MOSIS TINY FRAME PADS (28PC23x34 FRAME)
From: Nai Chi Lee
Date: Sun, 06 Dec 1987 03:34
Date: Sun, 06 Dec 1987 03:34
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In article <4218@venera.isi.edu>, sllu@venera.isi.edu (Lien Lu) writes:
> ... The other group
> of DRC violations has to do with P+ select layers (which are automatically
> generated by Magic) getting too close to transistor channels.
> There are 16 pieces of diffusion layers used as shields to block
> the bloating of P+ selects. These diffusions does not have to follow
> the rules.
I just manually corrected all the above 16 drc errors ("select must
be xx lambda away from transistor") for the nsf-padio.
Anyone who is interested can get it from me, so that I won't feel that
my effort was wasted :-)
Now for a question: can "padio" of TinyChip be used for standard frames?
I have already done so for "40P69X68", but those padio cells are so small
that I have to add spacers to satisfy pad-to-edge restriction.
--
Dr. Nai Chi Lee
CSNET: nclee@sbcs.csnet
ARPA: nclee%suny-sb.csnet@csnet-relay.arpa
UUCP: {allegra, hocsd, philabs, ogcvax} !sbcs!nclee
"It is difficult to make something foolproof because fools are so ingenious."
[Anon]
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!uunet!husc6!cmcl2!rutgers!sri-unix!ctnews!pyramid!prls!philabs!sbcs!nclee From: nclee@sbcs (Nai Chi Lee) Newsgroups: comp.lsi Subject: Re: MOSIS TINY FRAME PADS (28PC23x34 FRAME) Message-ID: <874@sbcs.sunysb.edu> Date: Sat, 5-Dec-87 22:34:27 EST Article-I.D.: sbcs.874 Posted: Sat Dec 5 22:34:27 1987 Date-Received: Sat, 12-Dec-87 12:37:53 EST References: <4218@venera.isi.edu> Organization: State University of New York at Stony Brook Lines: 24 Keywords: Magic DRC violations, I/O pad drivers, MOSIS, VLSI class Summary: corrected padio