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		      NEW BOOK ANNOUNCEMENT:


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		HARDWARE MODELING WITH VERILOG HDL
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				by

			 Eliezer Sternheim
		       Interpretive Systems

			   Rajvir Singh
		        Nexgen Microsystems

			   Yatin Trivedi
			 Sun Microsystems
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This is the first book about the Verilog Hardware Description Language
which has become a standard for designing digital systems and VLSI devices.
The book is primarily written for those who have prior knowledge of the
Verilog HDL and want to learn more about designing complex devices and large
systems.

This book is also useful to designers with no Verilog experience but with
exposure to other hardware description languages or high level programming
languages. A separate chapter is devoted to the introduction of Verilog HDL
with emphasis on the behavioral aspects of the language.

The book also contains a separate chapter describing some useful tips and 
techniques in modeling debugging. Two appendices give formal syntax of the
language and its reserved keywords.

The book contains the following chapters:

	1. Why Hardware Description Languages?
	2. Anatomy of the Verilog HDL
	3. Modeling a Pipelined Processor
	4. Modeling System Blocks
	5. Modeling Cache Memories
	6. Modeling Asynchronous I/O: UART
	7. Modeling a Floppy Disk Subsystem
	8. Useful Modeling and Debugging Techniques

	Appendix A: Verilog Formal Syntax Definition
	Appendix B: Verilog Keywords

Each chapter on modeling first describes a piece of hardware, then develops
and explains its Verilog model, and at the end, provides a complete listing
of the Verilog model. The stress has been to design a piece of hardware at
a higher level of abstraction which can be implemented at gate level by some
appropriate synthesizer.

Check with local bookstores or to order a copy of the book write to the publishers:

	Automata Publishing Company
	PO Box 50335
	Palo Alto, CA 94303, USA
	Fax: 415-855-9545
	Phone: 408-255-0705

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	VOLUME DISCOUNT AVAILABLE FROM PUBLISHER 
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The souce code for the models can be purchased from the publisher.


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DISCLAIMER: This posting is done as a favor to the authors and I have no
personal monetary benefits
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Shrenik Mehta
Sun Microsystems
shrenik@Eng.Sun.COM