Free WinEDA / PLD Con Evening Discussion

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1 total messages Started by John Cooley Fri, 21 Apr 1995 00:00

#1329

Author: John Cooley
Date: Fri, 21 Apr 1995 00:00

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         EDA After Hours with Richard Goering and Rita Glover
         ----------------------------------------------------

WinEDA '95 is offering a free, open discussion session for all (Windows &
UNIX based) EDA tool users on Wednesday, April 26, 6:00 - 7:30 p.m.,
Santa Clara Convention Center.  (There are two conferences going on at
this time: WinEDA '95 and PLD Con '95 -- both of which you have to pay to
enter -- this evening discussion is an open, free event.)

This is meant to be a user oriented session -- enjoy a beer and "speak out"
to a panel of EDA vendors, advocates, and other users about what you really
need and want in Windows-based EDA tools today and in the future.

  Moderators for the Evening are:
    Richard Goering of EE Times
    Rita Glover of EDA Today

  Session Chairman:
    Jeff Edson, Vice President, Intergraph Electronics

  EDA Panelists:
    Mark Miller, Vice President, Escalade
    John Birkner, Vice President, QuickLogic
    David Kohlmeier, Director of Marketing, Data I/O

  EDA Advocates and Users:
    John Cooley, Consultant and User Advocate
    Sean Murphy, President, Leader Murphy, Inc.
    Adam Levinthal, Director of Engineering, Silicon Gaming          


          WinEDA '95,  Santa Clara Convention Center
         Wednesday Evening, April 26, 6:00 - 7:30 p.m.

Make Richard Goering's "Top-Ten" list of issues and questions from users!
Send your provocative questions or burning issues about Windows-based EDA
tools to Richard Goering at "edausers@cmp.com".  The "Top-Ten"  list
will be the starting point for lively discussion!

*Session open to all users of EDA tools.  Need not be registered for 
conference to attend.  For information or a complete program guide for
WinEDA'95 and PLDCon'95, call 1-800-839-2429.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3349 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

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