Interrupts on IMB PC -- (386 DX 33 Mhz)

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1 total messages Started by nejib Sun, 27 Sep 1992 19:04

Author: nejib
Date: Sun, 27 Sep 1992 19:04

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I have a timer board ( Intel 8254) which generates interrupts (if you must
know, the cheap setup is as follows: the three counters of the 8254 are
cascaded and their final output is hooked to an 8255 I/O chip, on the same
board, which is hooked to IRQ7). The problem is that upon initialization the
counter's output goes from high to low and the PIC ( 8259 ) buffers (?) an 
interrupt. So, immediately after the IRQ7 is enabled an unneeded interrupt 
is generated.

My question is: Is there a way of telling the PIC (8259) to forget about
the last interrupt request on IRQ7; disabling the interrupt won't do
it, since, apparently, it is buffered.

Thanks in advance; and would you please answer me by e-mail, since I do
not read this group often.


                             --Nejib

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