Call for papers: Hardware Accelerators for VLSI Design

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1 total messages Started by Bill Baker Fri, 06 Nov 1992 20:39

#162

Author: Bill Baker
Date: Fri, 06 Nov 1992 20:39

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                            Call for Papers

                            Special Issue on

                 Hardware Accelerators for VLSI Design

VLSI DESIGN: An International Journal of Custom-Chip Design, Simulation and
Testing

A special issue of the VLSI Design Journal will be devoted to Hardware 
Accelerators for VLSI Design.  Topics of interest include, but are not 
limited to, the following:

	* Accelerators for logic simulation
	* Accelerators for analog simulation
	* Mixed analog/digital simulation acceleration
	* Parallel architectures for simulation acceleration
	* Placement, routing, and design-rule-check engines
	* Parallel, distributed simulation algorithms
	* Accelerators for VLSI testing and fault simulation

Instructions for Submitting Manuscripts

Manuscripts should be no more than 25 double-spaced pages (about 6000 words)
in lenth including all figures and references.  Papers must not have been
previously published or currently submitted for publication elsewhere.
Manuscripts should have a title page that includes the title of the paper,
full name(s) and affliation(s) of the author(s), complete physical and
electronic address(es), telephone number(s), and an abstract.

DEADLINES

	* Four copies of the full manuscript are due by March 1, 1993
	* Notification of acceptance is July 1, 1993.


Send Submissions and Questions to:

Dr. Ausif Mahmood, Guest Editor
School of Electrical Engineering and Computer Science
Washington State University at Tri-Cities
100 Sprout Road
Richland, WA 99352

Phone: (509) 375-9234
Email: mahmood@beta.tricity.wsu.edu


Dr. George W. Zobrist, Editor-in-Chief
Department of Computer Science
University of Missouri-Rolla
Rolla, MO 65401

Phone: (314) 341-4492
Email: c2816@umrvmb.umr.edu

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