🚀 go-pugleaf

Software Engineer

Responsibilities:

Develop partition, packing algorithms for CPLD/FPGA
Provide concurrent Engineering support for software development using
strong programmable logic device architecture evaluation knowledge.
Develop prototype place and route tools for new CPLD/FPGA architectures
Develop integrated timing driven optimization partitioning and place and
route flow

Education/Skills

MS or PhD in CS/EE or equivalent background
Two or more years developing software for one or more of the following
areas:

timing analysis
logic synthesis
logic optimization, place and route tools
CPLD/FPGA
Strong knowledge of C++ and Java and Windows and/or Unix

Famililiarity with OO programming, case tools and/or EDA software


Position #2:  Sr. Software Engineer

Responsibilities:

Develop Place and Route tools for programmable logic Devices
Develop Test suites for regression testing of place and route tools
Develop prototype place and route tools for new CPLD/FPGA architectures
Enhance existing logic synthesis, logic optimization and place and route
tools with timing driven capabilities

Education/Skills

MS or PhD in CS/EE or equivalent background
Two or more years developing software for one or more of the following
areas:

timing analysis
logic synthesis
logic optimization, place and route tools
CPLD/FPGA
Strong knowledge of C++ and Java and Windows and/or Unix

Famililiarity with OO programming, case tools and/or EDA software

Competitive salary and benefits packages available.  Will relocate you
to Colorado Springs.