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Article #493

Re: Dual Celeron's and SMP Performance Problems

#493
From: Totally Lost
Date: Fri, 28 May 1999 00:00
26 lines
2160 bytes
In article <7iln23$niq$1@sparcserver.lrz-muenchen.de>,
  kuhn@lpr.e-technik.tu-muenchen.de.nospam wrote:
> In comp.os.linux.hardware Totally Lost <idletime@my-deja.com> wrote:
>
> : What's the point ... apples and oranges comparisons are a waste of
> : time.
>
> Hey, you have started the discussion about
> Dual Celeron vs. Dual Pentium :-)

I started a discussion that at the same clock rate, a 128K L2
cache could have significant performance penalties comparied
to equiv processors with 512K L2 caches, expecially in dual SMP
configurations.

I was responding to the assertion that a 10 Celeron cluster
was somehow better than one top of the line 500MHz Xeon with
2MB of L2 ... clusters aren't SMP, they are tightly coupled
distributed processing. Each is optimized for extremely different
work loads, that the other will basically fall on it's face with.
There is absolutely no way to compare what is right or fast without
agreeing what the reference application is. Hence, apples and oranges.


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From: Totally Lost <idletime@my-deja.com>
Subject: Re: Dual Celeron's and SMP Performance Problems
Date: 1999/05/28
Message-ID: <7imbap$lqh$1@nnrp1.deja.com>
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