🚀 go-pugleaf

Chris Mauritz wrote:
> 
><food fight removed>
> 
> The bottom line from my limited experience with dual celerons and
> substantial experience with dual PPro's and PII/III's is that:
> 
> * The likely outcome is an increase in performance.
> * The degree of performance increase is application dependent.
> * Given "ideal" conditions, it's possible to get a degradation
>   in performance if the application needs the additional L2 cache.
> * Given those same "ideal" conditions, it may also be a problem
>   to use bona fide PII/PIII's.
> 
> I'm not sure why some folks are getting all worked up over this.


Well..

Intel has actively promoted the notion that Celerons are a cheap,
inferior product, not worthy of consideration for those doing "real"
computing.  Smp capability was hidden, and then when discovered, was
denounced, and practicers threatened with loss of warranty - even when
the capability is enabled by a jumper on an adapter (no
drilling/soldering - just throw a switch).  Now that the word is out
that one can purchase off-the shelf products, plug them in, and enable
this capability, and online reviews have appeared of dual Celeron
systems, there have been articles posted suggesting that the small cache
so cripples these processors that even though you can enable this
feature, why would any serious person want to - just go out and buy a
few Xeons with a couple MBs of cache if you want to do "real" computing.

I feel this is misleading.  While lack of the large cache may be
(probably/surely is) a hindrance in some situations, I suspect that
these situations are less common than Intel would have the general
public believe.  And then again, I could be all wet and have mud in my
eye.

I see a multi-tasking advantage.  I see Celerons as an economical
alternative to some higher cost solutions.  I think it is more useful to
post specific information about the observed practical limitations of a
particular setup, or practical methods to improve performance with given
hardware than to post a long theoretical diatribe about the terrible
hazards of Celeron smp.  Determining the practical limits would add
knowledge.

CB

> 
> C
> --
> Christopher Mauritz
> ritz@mordor.net


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