🚀 go-pugleaf

Good Post Suran. But I think your final assertion needs to be
qualified:

> ...someone who is running a dual PII, optimizing and writing parallel
> and distributed software scince some time and will definately UPGRADE
> to a newer dual celeron.

IF, AND ONLY IF, the working set is less than 128K, which could be a
difficult problem if they worked hard tuning the application just
to get it's working set below the 512K point on their PII system.

In article <374C1564.BF40EF52@gmx.net>,
  suran@gmx.net wrote:
>
>
> Rowan Hughes wrote:
> >
> > In article <7iette$6ge$1@nnrp03.primenet.com>, Rod Roark wrote:
> > >I must be dense.  After reading this a couple of times I still
don't
> > >understand: how can two Celerons be worse than one when each has
its
> > >own cache?  I don't see how an interrupt serviced by one would
cause
> >
> > Well i've certainly had this experience on dual/SMP machines,
> > although not on X86/linux.
>
> There are many thing that can go worse than an single-systems if not
> written with SMP's in mind.
>
> First Cache-Trashing: (big impact)
> 	If some processors happen to work on the same data and this data is
> 	smaller than a cache-line (512Byte? don't know for intel, only
guess.)
> 	if one processor updates only one byte the other has to trash this
line
> 	and (scince he is working on it) get it from the first one blocking
> 	the interface to the memory and IO (bus-architecture) wich is a real
> 	performance-blocker in SMPs (that's why big SMP's often have really
big
> 	cross-bared and interleaved memory interfaces with huge third-level
> caches.).
>
> Second Cache-Flushing: (even bigger)
> 	happens at Mutex-Locks(syncronization of multiple threads should as
> long as possible
> 	be handled without these) and propably interrupts (never gone this
far
> into the mashine
> 	to know about this for shure).
>
> Third Memory-Access:
> 	Multiple processors have to syncronize and share a single (on i386
> REALLY NARROW)
> 	memory-interface and all this IO-devices. If more than one processors
> want sth. to
> 	chew on they have to wait for each other and are probably sitting
> pretty idle
> 	(especially on large data-sets even an older alpha with say, 70% the
> fp-power
> 	of the compared intel can rush away because of this, and this is what
> his graph
> 	showed and it has a REALLY HUGE IMPACT scince both processors may end
> up cooling
> 	down and waiting for each other but that's more a problem of i386
> against others
> 	that is only experienced much clearer on SMP's.).
>
> 	...someone who is running a dual PII, optimizing and writing parallel
> and distributed
> 	   software scince some time and will definately UPGRADE to a newer
> dual celeron.
>
> ---
> Suran@gmx.net
>


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