🚀 go-pugleaf

Dear friend, niessene@natlab.research.philips.com

I have just seen your post (1999/06/17) about PCI burst performance. I
am facing the same problem. Rather the two same problems: missing PCI
burst and unexpected bad PCI read performance. Write PCI bandwidth is
never better than 44MBs, and read PCI bandwidth then 9MBs!!!! Your PCI
analyzer tables are similar to ours. Amazing figures.

I am accessing to PCI card by memory mapping (ioremap, memcpy_toio,
memcpy_fromio, ...). On a x86 box these operations are direct "memcpy()"
calls and if you see the "include/asm-i386/string-486.h", the macro
"__memcpy_by4" executes "movl" statements (double word). In the new
kernels it seems there is a new MMX-3DNow version of the "memcpy()" (for
AMD guys). The MTTR registers are Intel specific and they are only
useful for write caching (I think so...).

In my opinion, the problem is not OS-dependent. Rather is a chipset
problem. I have looked through some datasheets: Intel 440BX and Via
MPV3. You can check Via MPV3 chipset has a lot registers tunning the PCI
operation: PCI write and read caching, wait states, burst enable, ...
Opposite, 440BX has an little configuration capability.

Next days, I am going to install an AMD-VIA box trying to get a best
performance. If you are still interested I will tell you the results
(although, the VIA MPV3 datasheet is a reference manual, lacking a good
functional description.

On the another hand, I would like to know if you has some information
about this topic.

Best Regards,


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