🚀 go-pugleaf

>   How are the page tables organized in Mach 2.6?  Are there any studies of TLB
>   miss rates at the different levels of the page table?  How much does a TLB
>   miss at each level cost?
>   Thanks.
>       Amer
>   --
>   ---------------------------------------------------------------------------
>   Amer Diwan					School of Computer Science
>   Fox Project					5000 Forbes Avenue
>   adiwan@cs.cmu.edu				Carnegie Mellon University
>   (412) 268-3066                                  Pittsburgh, PA 15213
>

We have written a couple of papers on this subject.  The papers compare
page table structure of Mach 3.0, OSF/1 and Ultrix and measure (through
hardware monitoring) the cost to handle different types of TLB misses.
The experiments were run on a DECstation 3100 with a MIPS R2000
processor that requires software management of TLB misses.

Some of our findings include:

o The cost to handle different types of misses varies dramatically.
  A miss on a level 1 user PTE can be handled in only about 20 cycles,
  but level 2 PTEs misses take over 300 cycles to service.

o Systems like Mach 3.0 stress the TLB much more than monolithic-kernel
  operating systems.  A system that is more "decomposed" into separate
  user-level services tends to see large increases in the very costly
  level 2 PTE misses.  The difference can add seconds to the run time...

Details can be found in:

	ftp ftp.eecs.umich.edu
	cd pub/os_arch/

-----------------------------------------
Rich Uhlig (uhlig@eecs.umich.edu)
U of M Advanced Computer Architecture Lab