MACH on Intel-Hypercube

Article View: comp.os.mach

Article #1315

#1315

From: Manolis Tsangaris
Date: Thu, 08 Mar 1990 16:48

16 lines
1301 bytes

Is there a port going on? I saw nothing about the (IPSC/2) Hypercube, in the
recent MACH newsletter.

It seems that MACH expects a uniform and equally accessible by all processors
physical memory (pmap interface).  People at Rochester have used the pmap
interface to support Non Uniform Access Memory (The ACE multiprocessor and the
Butterfly), but IPSC/2's memory is completely partitioned among the processors
(i.e. every memory module is local to each processor).

Since IPSC/2 is a "shared nothing" multiprocessor, is it advisable to run a
single MACH kernel over its 32 (or less) processors?  The alternative solution
would be to treat hypercube as a super fast distributed system, with one MACH
kernel per processor. But this would make expensive things like task migration
(how about TLB consistency!).

--mt

Technical Details

Message-ID: <9902@spool.cs.wisc.edu>

Path:

arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!uwm.edu!cs.utexas.edu!tut.cis.ohio-state.edu!ucbvax!decwrl!dogie.macc.wisc.edu!uwvax!cleo.cs.wisc.edu!mt

Show Full Headers

Complete Article Headers

Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!uwm.edu!cs.utexas.edu!tut.cis.ohio-state.edu!ucbvax!decwrl!dogie.macc.wisc.edu!uwvax!cleo.cs.wisc.edu!mt
From: mt@cleo.cs.wisc.edu (Manolis Tsangaris)
Newsgroups: comp.os.mach
Subject: MACH on Intel-Hypercube
Summary: Multiprocessors, Hypercube
Message-ID: <9902@spool.cs.wisc.edu>
Date: 8 Mar 90 16:48:12 GMT
Sender: news@spool.cs.wisc.edu
Distribution: usa
Organization: U of Wisconsin CS Dept
Lines: 16