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Article #5362Re: Maximum DMA on XT and AT
From: Antony Hodgson
Date: Fri, 22 Mar 1991 00:19
Date: Fri, 22 Mar 1991 00:19
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1759 bytes
In article <1991Mar21.151029.25820@sparrms.ists.ca> ddr@sparrms.ists.ca (Dave Rajnauth) writes: >I have been reading the the XT only supports under 0.5Mbyte/sec >DMA although the DMA chip supports over 1Mbyte/sec. It was suggested >that this was because of the 8088 being able to access the bus during >the DMA cycles and memory refresh (which uses DMA channel 1). > >Does anyone know how to bump up this DMA speed? Should I expect >this speed on the AT? How can I get the max. DMA speed from >a XT or AT? > In single-byte transfer mode, the CPU gets access to the bus between DMA cycles. If I remember rightly, a 1-byte transfer takes 6 clock cycles (1.2 us on 4.77MHz machines) followed by 4 clock cycles where the CPU has bus access (0.8 us). The minimum cycle time in this mode is therefore 2 us/byte (=500kB/s). This rate scales with bus bandwidth (i.e., a 20MHz bus will give you about 2MB/s). It is possible to play a number of fancier games to use almost the whole bus bandwidth, but if anything goes wrong with the transfer, your CPU may never get control of the bus back. You can imagine how little useful work it can do without access to memory or video cards or anything else! Good luck! Tony Hodgson ahodgson@hstbme.mit.edu
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!snorkelwacker.mit.edu!bloom-picayune.mit.edu!ahodgson From: ahodgson@athena.mit.edu (Antony Hodgson) Newsgroups: comp.os.msdos.programmer Subject: Re: Maximum DMA on XT and AT Message-ID: <1991Mar22.001921.11608@athena.mit.edu> Date: 22 Mar 91 00:19:21 GMT References: <1991Mar21.151029.25820@sparrms.ists.ca> Sender: news@athena.mit.edu (News system) Organization: Massachusetts Institute of Technology Lines: 27