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In article <Pine.SOL.3.91.960225103721.16366A-100000@hamlet.uncg.edu>, b_lee2@hamlet.uncg.edu says...
>
>
>Hi, folks:
>
>I wrote a DOS program in Borland C++, because my interrupt service routine
>block OS for 3 millisecond of every 5 millisecond, I think this cause 
>bios no time to serve and check keyboard buffer, which cause keybord buffer
>overflow.
>
>Two questions:
>1. related to process of bios handler keyboard buffer, when IRQ1 generate 
>a interrupt, but has not finished its ISR, can other IRQ, such as IRQ7 
>generate a interrupt in between ? How can keyboard buffer overflow happen ?
>
>2. cli and sti will disable and enable all IRQ, is there a instruction which
>will only disable and enable one specific IRQ, like IRQ7.
>
>structure of my program
>
>int main(void)
>{
>        InstallExternalTimingIRQ7ISR()
>
>        while( waitkey() )
>        {
>                doKeyboardInput_ScrOutout();
>        }
>        
>        ReinstallOldIRQ7ISR();
>}
>My interrupt happens every 5 ms and program need 3 ms to finish its ISR,
>during this time, I use cli and sti to protect its service, how will this 
>affect keyboard interrupt ? The interrupt I used is external circuit 
>generate 5 ms interrupt connect to IRQ7.
>
>Thanks folks, this is urgent for me, please send me a mail.

Hardware interrupts are first fielded by the PIC (Intel 8259A Progammable
Interrupt Controller). This thing acts as a sort of receptionist for the
CPU. It accepts up to eight distinct interrupts and can mask (ignore) 
interrupts individually. It responds to each unmasked interrupt and 
forwards it to the CPU, provided no other interrupt of higher priority
is being serviced at that moment, Basically, the lower the IRQ number,
the higher the priority.Timer - IRQ0, Keyboard - IRQ2, etc...
To answer your question, you can mask individual interrupts on the PIC.
This isn't the correct thing to do. The CPU automatically disables all
interrupts when it transfers control to the service routine for the current
interrupt. During the servicing of the interrupt, the PIC inhibits further
interrupts of the same or lower priority, but higher priority interrupts
are still acknowledged if the interrupt flag is set. To allow this to
function correctly, your ISR *MUST* reenable interrupts with an STI
immediately, before it begins servicing your interrupt.  This allows the
other devices to function properly.