🚀 go-pugleaf

In article <1991Sep1.200028.16596@aber.ac.uk> pcg@aber.ac.uk (Piercarlo Grandi) writes:

>    Amazing facts: the maximum bandwidth of the MCA bus when running at full
>    tilt in 32 bit mode is under 40MB/s; to have 100MB/s of transfer rate
>    *to memory* would require dozens of megabytes of requires hundreds of MB
>    of 4-way interleaved 20-30ns RAM; to be able to consistently get 20MB/s
>    on a TCP/IP link would require, assuming an overhead of 4 instructions
>    per byte passed thru (wildly optimistic, just consider checksumming), a
>    80Mhz CPU.

That contradicts what I have read about the MCA bus.  The 40MB/s is for
streaming data mode (burst mode is at 20MB/s).

However the MCA bus support data-multiplexing, that uses the address lines
as data to give a 64 bit wide transfer.   It's not limited to using just
the data lines.

My information is from a book called "The Micro Channel Architecture
Handbook" written  by Chet Heath (one of the MCA designers, so there is a
vested interest there).

This books shows that when multiplexing using the streaming data mode the
transfer rate is 80MB/sec.  (NCR is claiming that speed on their new MCA
bus-based multi-processor '486 boxes).

One paragraph (paraphrased to conserve space) notes that the bus cycle time
is 100ns in these specifications, but the bus specs would allow a 50ns
cycle time.   At that time the throughput could approach 160MB/sec.
There is nothing to note that this has been done, though they did note that
the "model 70 E80 systems implement at 62.5 ns cycle".




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Bill Vermillion - UUCP: ...!tarpit!bilver!bill
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