🚀 go-pugleaf

Volume: 21, Issue: 2, Wed Mar 27 15:54:29 EST 1991

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| TODAY'S TOPICS |
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(1) Workshop for Integrated Engineering Workstations
(2) Performance of Distributed DES Algorithms
(3) WANTED: Sports Simulations
(4) DISCUSSION: comp.lsi
(5) CALL: Parallel & Distributed Processing

* Moderator: Paul Fishwick, Univ. of Florida
* Send topical mail to: simulation@bikini.cis.ufl.edu OR
  post to comp.simulation via USENET
* Archives available via FTP to bikini.cis.ufl.edu (128.227.224.1).
  Login as 'ftp', use your last name as the password, change
  directory to pub/simdigest. Do 'type binary' before any file xfers.
* Simulation Tools available by doing above and changing the
  directory to pub/simdigest/tools. 



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>From ABURDENE@coral.bucknell.edu Thu Mar 21 10:38:51 1991
Date: Thu, 21 Mar 1991 10:38 EST
From: ABURDENE@coral.bucknell.edu
Subject: NSF sponsored Workshop at Bucknell
To: fishwick@fish.cis.ufl.edu
X-Envelope-To: fishwick@fish.cis.ufl.edu
X-Vms-To: IN%"fishwick@fish.cis.ufl.edu"
X-Vms-Cc: ABURDENE


         Workshop on Integrated Engineering Workstation
             for Science and Engineering Faculty
 
                     Bucknell University
 
 
The purpose of this workshop is to offer undergraduate faculty the opportunity
to learn about several types of Integrated Engineering Workstations (IEW's) of
varying complexity and capabilities.  An IEW consists of a microcomputer
interfaced to data acquisition, test and control instrumentation.
Through experimental hands-on experiences in laboratory sessions, the
participants will also develop an experiment and course materials for
their own laboratory.  Two similar one week sessions will be offered on:

 
                               July  7-12, 1991
                               July 14-19, 1991
 
at:
Bucknell University
Electrical Engineering Department
Lewisburg, PA, 17837
(717)-524-1234
 
PARTICIPANT SUPPORT:
 
     The workshop is sponsored by the National Science Foundation and Bucknell
University.  There are no registration fees or tuition expenses for this
workshop.  Housing will be in air-conditioned residential areas on Bucknell's
picturesque campus.  Housing and meals in our cafeteria will be covered by the 
National Science Foundation.  Participants are responsible for their travel
and other indidental expenses.

 
 
PARTICIPANT SELECTION:
 
     The selection process will rely heavily on nominations by department heads 
or chairs of the participant's home institution.  The workshop is intended for
teachers of science and engineering in the US who are committed to
undergraduate education and who have not yet had extensive exposure to
integrated engineering workstations.
 
     The participants will develop an experiment and class material for 
implementation at their home institutions.  We will sustain the development of
these experiments by providing information through an electronic mail network.  
(Reached at mastascu@bucknell.edu)
 
     The participants selected are required to submit a project proposal 
outlining the work to be undertaken after the workshop.  We will be pleased 
to help participants formulate their proposals.
 
 
WORKSHOP OUTLINE:
 
     We will begin with fundamental computer concepts, proceed to workstation 
and instrumentation concepts, and conclude with applications.  Ample time will 
be provided for planning and construction of the participants' projects.
 
     Our IEW's include personal computers with data acquisition and control  
instruments, including Hewlett Packard control computers, IBM PC's, IEEE-488 
instrumentation and a lab with an ethernet network of computers using IEEE-488 
instruments for distributed data acquisition and control.
 
 
WORKSHOP FACULTY:
 
Maurice F. Aburdene, Professor of Electrical Engineering and Computer Science 
 
William J. Snyder, Professor of Chemical Engineering
 
Edward J. Mastascusa, Professor of Electrical Engineering
 
 
WORKSHOP ASSISTANTS:
 
Thomas Thul, Electronic Technician
 


             WHERE TO SEND APPLICATION FORM
 
The application form may be returned by electronic mail to:
 
                  mastascu@bucknell.edu
 
                  or through US Mail to:
 
E. J. Mastascusa
Electrical Engineering Department
Bucknell University
Lewisburg PA  17837
 
 --------------------------------------------------------------------------
                      APPLICATION FORM
 
Name of Applicant:
 
College or University:
 
Mailing Address:
 
 
 
Session 1 (July  7-12, 1991):
 
Session 2 (July 14-19, 1991):
 
Department Chair:



 
Address of Department Chair and Applicant:
 
 
 
Special Needs:
 



 
END OF APPLICATION FORM




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Date: Thu, 21 Mar 91 16:35:53 EST
From: nimish@cat.syr.edu (Nimish Radia)
Subject: Need info. on tools to do performance analysis of distributed discrent-event simulation algorithms
References: 
Sender: 
Followup-To: 
Distribution: na
Organization: Syracuse University
Keywords: 
To: comp-simulation@rutgers.edu

hi --

The following question/inquiry might have been asked to this
group before, but as a new user I do not have any knowledge
of it. I will appreciate any information/help I can get.
Thank you very much in advance.

I am looking for a software package to measure the performance
of distributed discrete-event simulation algorithms. I want the
package to allow me to do following things.

(1) Allow to model multiple channels (input and output) for each logical 
    process.
(2) Allow to define a varible processing time for events at each 
    logical process. 
(3) Allow to model multiple logical processes per server (or node in 
    the distributed system).
(4) Allow multiple servers.
(5) Allow to define some relationship between events at each logical
    process. Depending upon this relationship, allow conditional
    simulation of events. This means that some events on some input
    of a logical process can be simulated only if some condition is satisfied 
    for the events on the other inputs of the logical process.

If anybody has any knowledge of a package which I can use/get, please 
send me an email at nimish@cat.syr.edu.

Thank you.

 --nimish radia


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To: comp-simulation@uunet.UU.NET
Path: pdxgate!eecs.cs.pdx.edu!jayward
From: jayward@eecs.cs.pdx.edu (Jay Ward)
Newsgroups: comp.simulation
Subject: rec.sport.basketball
Date: 25 Mar 91 01:43:37 GMT
Sender: pdxgate!news@uunet.UU.NET
Reply-To: jayward@eecs.cs.pdx.edu (Jay Ward)
Organization: Portland State University, Portland, OR


I am looking for some information/references on sports simulations.  I am not
interested in game type simulations, but real statistical analysis of past 
game records and player stats.  Any help here? Source code, book titles,
anything would be appreciated.


 ----------------------------------------------------------------------------
Jay Ward --> jayward@eecs.cs.pdx.edu | if (TrailBlazers > Opponents)      
"                 " - Marcel Marceau | 		TrailBlazerWins++;
 ----------------------------------------------------------------------------


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Newsgroups: comp.simulation
Path: veit
From: veit@du9ds3.uni-duisburg.de (Holger Veit)
Subject: CFD: comp.lsi.cat (CA-testing of VLSI circuits)
Followup-To: news.groups
Summary: cfd,comp.lsi.cat
Keywords: comp.lsi.cat
Sender: unidui.uni-duisburg.de!@unidui.uni-duisburg.de
Organization: Rechenzentrum Uni-Duisburg
Date: 22 Mar 91 08:06:31 GMT
Apparently-To: comp-simulation@unido.uucp



CALL FOR DISCUSSION - please respond (to news.groups)

NAME: 
    comp.lsi.cat

STATUS: 
    unmoderated

CHARTER:
    "A major problem, one which is growing in importance, is testing.
    Problems associated with testing of digital logic have been with
    us for as long as digital logic itself has existed." [Alexander 
    Miczo, Digital Logic and Simulation, 1986]

    During the last 25 years, an immense number of techniques,
    methods and algorithms to guarantee the proper testing of 
    electronic devices have been introduced. Testing is an important
    subject to many major international conferences (e.g. ITC, ETC, 
    DAC, EDAC, ICCD, ICCAD, FTCS, ISCAS) and journals (e.g. JETTA, 
    IEEE Trans. on CAD, IEEE Trans. on Comp.). Thus, testing is 
    an area of highest relevance to many CAD researchers and 
    professionals.

    This newsgroup is intended to cover all aspects of the testing of
    electronic circuits such as (but not restricted to)
      *  Testing of Digital and Analog Devices
      *  Automatic Test Pattern Generation
      *  Fault Modeling and Fault Simulation
      *  Design for Testability
      *  Scan Design and Built-in Self Test
      *  PCB-Test and Boundary Scan
      *  Design Verification

    Important topics are
      * Announcements (conferences, workshops, special issues)
      * Books on testing
      * Standards
      * Tools
      * Benchmarks
      * Questions and answers
      * Discussions concerning technical or algorithmic problems

WHY A NEW GROUP:
    The ever increasing number of publications on testing shows a
    vivid and growing interest in that subject. A newsgroup on 
    testing will stimulate and accelerate the exchange of related 
    information among interested network users. It makes it easier 
    to recognize current trends in testing, especially 
    for novices. We believe that there will be enough traffic in
    the new group to justify its creation.

SCHEDULE:

1. DISCUSSION
    The discussion period begins on monday, march 25.
    It ends on tuesday, april 23.
    (possibly continued by email)

2. VOTE
    If the discussion is successful, we will send the call for votes
    on monday, april 29. This posting will contain all necessary 
    information how to vote. The rest of the procedure will follow
    the rules to create new groups (see news.announce.newusers for details).

Please respect that the follow-up of a CALL FOR DISUSSION is news.groups.
Send your opinions to this call - otherwise there will be no comp.lsi.cat.
All comments are welcome.

AUTHORS:

Nikolaus Gouders (gouders@du9ds3.uni-duisburg.de)
Holger Veit (veit@du9ds3.uni-duisburg.de)
University of Duisburg, Germany



 --
|  |   / Holger Veit             | INTERNET: veit@du9ds3.uni-duisburg.de
|__|  /  University of Duisburg  | BITNET: veit%du9ds3.uni-duisburg.de@UNIDO
|  | /   Fac. of Electr. Eng.    | UUCP:   ...!uunet!unido!unidui!hl351ge
|  |/    Dept. f. Dataprocessing | 




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Newsgroups: comp.simulation
Path: hbchen
From: hbchen@evax.uta.edu (Hsing B Chen)
Subject: call for paper - 1991 SPDP 
Expires: July 1991 
Date: Tue, 26 Mar 91 16:38:55 GMT
Organization: Computer Science Engineering Univ. of Texas at Arlington
Keywords: simulation and performance modeling, parallel and distributed
Sender: shirazi@evax.uta.edu (Behrooz Shirazi)
Summary: Third Symposium on Parallel and Distributed Processing 
Apparently-To: uunet!comp-simulation

processing  


      ============================================================
  
                    ******* CALL FOR PAPER *******

       Third IEEE Symposium on Parallel and Distributed Processing
              Dallas, Texas - December 1 - 5, 1991

      =============================================================


           
The Third IEEE Symposium on Parallel and Distributed Processing
Dallas, Texas - December 1-5, 1991

The symposium will provide a forum for the presentation and exchange
of current work on various topics in parallel and distributed
processing including, but not limited to, the following areas:

Computer Architecture	 	Programming Languages
Operating Systems		Neural Networks
Interconnection Networks   	Database and Knowledge-base Systems
Artificial Intelligence		Parallel Algorithms
VLSI Systems Design		Simulation and Performance Modeling
Distributed Computing		Image Processing
Scheduling

Authors are invited to submit complete, original, and previously
unpublished papers reflecting their current research results. Any
paper submitted to the Symposium should not be submitted to any other
conference.  All submitted papers will be refereed for quality and
originality.  The program committee reserves the right to accept a
submission as a long, short, or poster presentation paper.  All 
accepted papers will be published in the symposium proceedings.

Manuscripts should be double spaced, should include an abstract, and
should be limited to 5000 words (about 20 pages).  The contact authors
are requested to list e-mail addresses if available.  Please submit 10
copies of the complete paper to a program chair in your geographical
area listed below.  Papers should reach a program chair no later than
May 31, 1991.   Due to timing limitations, this deadline will be
strictly observed.  Papers received after May 31st will not be 
considered.  Authors will be notified of acceptance/rejection of
their papers by August 9, 1991. Final camera-ready papers are due
September 9, 1991.

Tutorials & Panels: Please submit proposals including title, abstract,
biography, and a list of panel participants by May 31, 1991 to one of
the program chairs in your geographical area.

Co-Program Chairs

North and South America:

Vijaya Ramachandran               OR    Greg Pfister
Department of Computer Sciences         IBM Corporation
The University of Texas at Austin       11400 Burnet Road
Taylor Hall 2.124                       L45/820, 2812
Austin, TX 78712-1188                   Austin, TX 78758
U.S.A.                                  U.S.A.
(512) 471-9548                          (512)823-1589
spdp@cs.utexas.edu			pfister@austin.iinus1.ibm.com

Europe and Africa:

Ian Watson
Department of Computer Science
University of Manchester
Oxford Rd.
Manchester M13 9PL
England
+44 61 275 6248
iwatson@cs.man.ac.uk

Asia and Australia:

Makoto Amamiya
Department of Information Systems
Graduate School of Engineering Sciences
Kyushu University
6-1 Kasuga-koen Kasuga
Fukuoka, 816
JAPAN
+81-92-573-9611
amamiya@is.kyushu-u.ac.jp

Conference Officers:

Chair of Steering Committee:
Behrooz Shirazi, Univ of Texas-Arlington, USA

Steering Committee:
Said Bettayeb, LSU, USA 
Prasenjit Biswas, TI, USA
Eliezer Dekel, Univ of Texas-Dallas, USA
Ali R. Hurson, Penn State U, USA 
Krishna Kavi, Univ of Texas-Arlington, USA
Ioannis Tollis, Univ of Texas-Dallas, USA 

General Chair:
Sartaj Sahni, Univ of Florida, USA

Program Committee:
Hosame Abu-Amara, Texas A&M, USA
Tadashi Ae, Hiroshima Univ, Japan
Tilak Agerwala, IBM Corp, USA
Laxmi Bhuyan, Texas A&M, USA
Bill Carroll, Univ of Texas-Arlington, USA
Harvey Cragon, Univ of Texas-Austin, USA
John Feo, Lawrence Livermore, USA
Joydeep Ghosh, Univ of Texas-Austin, USA
Susanne Hambrusch, Purdue Univ, USA
A(Tony).J.Hey, Southampton Univ, England
Ray Liuzzi, RADC-AFOSR, USA
Michael Merritt, AT&T Bell Labs, USA
Les Miller, Iowa State Univ, USA
Rikio Onai, NTT, Japan
Simin Pakzad, Penn State Univ, USA
Ian Parberry, Univ of North Texas, USA
Behrooz Parhami, Univ of California-SB, USA
Girish Pathak, Xerox, USA
Greg Plaxton, Univ of Texas-Austin
Donna Quammen, George Mason Univ, USA
Alejandro Schaffer, Rice Univ, USA
H.J. Siegel, Purdue Univ, USA
Barbara Simons, IBM Almaden, USA
Hal Sudborough, Univ of Texas-Dallas, USA
Kam-Fai Wong, ECRC GmbH, Germany
Yoshinori Yamaguchi, ETL, Japan
Yanjun Zhang, Southern Methodist Univ, USA

Finances: Randy Chow, CIS, Univ of Florida, USA
Publicity: Sanjay Ranka, Syracuse, USA
Local Arrangements: Y. Paul Chiang, Texas Instruments, USA
Registration: Pearl Wang, George Mason Univ, USA
Publications:  Sadegh Davari, Univ of Houston-Clear Lake, USA
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END OF SIMULATION DIGEST
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