🚀 go-pugleaf

> From: dsims@leo.ece.uc.edu (D. Lyle Sims)
> 
> I'm curious what people use as specification languages for hardware
> description languages such as VHDL.  Gate level descriptions?  Anything
> else?  Anything with a formal syntax and semantics?

Like a large part of industry, we use Verilog as our simulation language
for the actual ASICs themselves and systems simulation.  Later on we
use Synopsys to convert the behavioral code into gates.

We chose this path because most ASIC vendors support it and all the software
tools involved have at least most of the major bugs found and fixed.  There
was a real fear of chosing a cheaper non-standard set of software tools
and then actually paying more for the tools with engineering's time chasing
bugs.

I know it's not terribly exciting and exotic to say you're using what everyone
else is, but we're paid to design hardware; not CAD tools!

					- John Cooley
					  ASIC Designer & CAE Grunt
					  Sequoia Systems, Inc.
					  Marlboro, Massachusetts, USA


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