🚀 go-pugleaf

In article <4dos4l$ra9@engnews1.Eng.Sun.COM>, clamage@Eng.Sun.COM (Steve Clamage) writes:
> I have longer experience with non-RISC implementations than with RISC
> implementations. It is common for non-RISC implemenations not to have
> a recognizable function preamble or postamble. There are not just two or
> three possible instruction sequences making up function entry and exit --
> there are dozens or even hundreds of possible sequences. If you standardize
> on recognizeable entry and exit sequences you take a noticeable performance
> hit, particularly on popular benchmark programs.

I have quite a bit of experience designing and implementing compilers and
programming tools (such as debuggers) on both RISC and non-RISC
architectures.  What Steve says is correct, but more importantly, it is not
limited to non-RISC architectures.  RISC compilers are becoming ever more
aggressive at optimization, and one of the areas that gets increasing
attention is function entry and exit.

Even without optimization, function entry and exit on many RISC machines is
not limited to a few recognizeable sequence of instructions.  Register
saving and restoring, for instance, can add lots of instructions to the
preamble or postamble.

But when you factor in optimizations such as sinking register saves and
hoisting register restores, moving user instructions into the preamble,
speculative execution of instructions, and so forth, the number of possible
sequences is infinite.

Now weigh against that the benefit, if there is any, of allowing an
exception to propagate out of a signal handler.  Does it buy you enough to
*require* RISC compilers to throw away huge performance gains?  Not in my
opinion.

-- 
Bill Leonard
Harris Computer Systems Corporation
2101 W. Cypress Creek Road
Fort Lauderdale, FL  33309
Bill.Leonard@mail.hcsc.com

These opinions and statements are my own and do not necessarily reflect the
opinions or positions of Harris Computer Systems Corporation.

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