🚀 go-pugleaf

In article <6578@armltd.uucp> astevens@armltd.co.uk (Ashley Stevens) writes:
>In article <1992Sep11.193305.20265@rhrk.uni-kl.de> m_sattle@tangram.informatik.uni-kl.de (Matthias Sattler) writes:
>
>
>>
>>I just replaced the 36 MHz quarz on the board of my A5000 by a 60 MHz one. This
>>had several results on my A5000.
>>1.) The VIDC is clocked faster so I could do 1024x768 60Hz (if your vidc
>>can do this)
>>2.) Mode 31 is 93 Hz (if your monitor can do this...)
>>3.) 800x600 256 Colours isn't possible any more
>>4.) There are problems with very low-res modes like mode 0, but I don't
>>know why
>>5.) The computer gets remarkably faster... >22000 Dhrystones in mode 21, 28 
>>    (with CPU 30 MHz) and I don't know why as well.
>
>The 36MHz clock also clocks the memory system. It's divided by 3 inside MEMC
>(effectively). So using a 60MHz clock means you are now running your memory
>system at 20MHz. Obviously this has a beneficial effect on your machine
>speed...if it continues to work.
>
I assume this is why the A3/4xx series have an 8 Mhz bus with a 24 Mhz
VIDC clock. What happens when a VIDC enhancer is used with these machines?
Does the MEMC now divide the higher clock by a higer number? If so then is
this division programmable?

Sorry to ask so many questions but I didn't realise that the memory
speed was related to the VIDC clock and would really like to know
how it all works.

Perhaps it is different on the older machines?

>
>___________________________________________________________________________
>Ashley Stevens, Design Engineer, Acorn Computer       astevens@acorn.co.uk      
>Temporarily encamped at ARM Ltd...                    astevens@armltd.co.uk


-- 
Sim. ----------------------------------------------------------- Simeon Walker,
----------------------------------------- Department of Electrical Engineering,
D.S.Walker@bradford.ac.uk -------------------- University of Bradford, England.