🚀 go-pugleaf

  I don't have an Archie myself but have used them quite a lot in the past.
I was recently mucking about with a friend's A5000, trying to find the new
instructions that turned the cache on and off. I found them, they were
co-processor instructions with the processor itself as (I think) number 0.

  Anyway, as I was disassembling away I found a new instruction (well, I had
never come across it before). It was 'SWP' and I imagine it swaps registers
with registers, maybe with memory as well? I can't remember. If it does
reg<->mem as well, and is uninterruptable, perhaps it is for use as a
semaphore in multi-processor systems?

  I worked out how it fitted into the instruction set, it is where an
illegal instruction was previously. I think it might have been due to only
four bits for a register shift, five bits for an immediate - hence an extra
bit which would have to be 0 for a normal instruction. I can't really
explain this very coherently but someone will know what I mean!

  I then wrote a program to generate all possible versions of this
instruction, but I didn't print them out... Anyway, it didn't help me work
out what they actually did (if I had my own A5000 I would spend some more
time on it, but I haven't and I'm just interested)

  Of course I won't be the first person to notice this so I wondered, could
someone post some info on this, and also on the co-processor instructions
relevant to the CPU itself?

  Another thing - RiscOs (being quite well designed as it is) has certain
ways of doing things which leads me to ask the question: When I do ...
  *memoryi 03800000 (Is it *memoryi? Is 03800000 ROM? Do I need my own
Archie?)

  ... and a coprocessor instruction is found, which module decodes it? Now
if I wrote Risc-Os, I would get the ARM3 support module to decode the
instructions, and I would get a floating point emulator to decode the FPU
instructions. That way, it's nicely modular and extensible.

  Now, I didn't write Risc-Os, and as I remember, the FPU decoding is done
in the debugger. I looked through the ARM3 support module and found some
text relating to the cache instructions, but not all of them. I couldn't
find any in the debugger.

  If I sound a little vague, please understand that I didn't have all day
to sort this out, and it was two months ago!

Andrew.

ps. Nothing to do with my post, but just to pour petrol on the flames, I'm
gonna buy a 486 PC cos I can get more power for less money, and the screen
doesn't blank when I access the disk drive :-) So if Acorn are listening
(and I think they are!) I think you have a well-defined problem on your
hands. I wonder if someone could write RiscOs for a PC? Or an Archimedes
emulator, now that would be amusing...