Article View: comp.sys.acorn.tech
Article #224RISCiX implementation
From: mhw
Date: Wed, 07 Oct 1992 10:09
Date: Wed, 07 Oct 1992 10:09
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1954 bytes
Does anyone know the details of how Acorn managed to get RISCiX to work? (Apart from a couple of guys at Acorn who did the hacking!) There seem to be a number of conflicts between the architecture of the ARM and the assumptions that BSD makes about the machine it will run on. For example: * BSD prioritises interrupts and disables all interrupts below a certain priority to acheive mutual exclusion (using x=spltty(); ...; splx(x);). The ARM doesn't prioritise interrupts unless you start twiddling bits in the IOC's interrupt mask. * BSD uses one stack (if I remember rightly); the kernel and interrupt handlers use the user mode stack to hold temporaries and such. The ARM gives the kernel, IRQ and FIQ handlers separate stack pointers which, while looking like a good idea, forces the kernel to allocate memory for two or more stacks rather than one. * The kernel executes from virtual (i.e. logically mapped) memory. On ARM based machines this could be inefficient as the MEMC would have to be reprogrammed to page the interrupt handler in (for example) and it would seem more logical to place the kernel in the physical memory space. * Is MEMC's operating system mode used? (The one that stops access to IO devices while leaving the processor in SVC mode.) * 32k is a huge page size for a Unix system; what effect does this have on the size of executables and how does the vm system cope with it? Anyone care to illuminate the grey areas? -Mark. -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Mark H. Wilkinson (mhw@minster.york.ac.uk)
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Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!uknet!yorkohm!minster!mhw From: mhw@minster.york.ac.uk Newsgroups: comp.sys.acorn.tech Subject: RISCiX implementation Message-ID: <718452550.20599@minster.york.ac.uk> Date: 7 Oct 92 10:09:10 GMT Organization: Department of Computer Science, University of York, England Lines: 35