Article View: comp.sys.acorn.tech
Article #450Re: 'volatile' in Norcroft/Acorn C
From: Mark Taunton
Date: Wed, 30 Sep 1992 13:11
Date: Wed, 30 Sep 1992 13:11
45 lines
2445 bytes
2445 bytes
Clive Jones writes:
>Hmm. I've just got my hands on a draft ANSI C standard, and it's quite
>clear, unfortunately, that an implementation is under no obligation at
>all to do this, however:
>
>It would be very nice if the compound assignment operators (+=, -=,
>*=, etc.) were atomic if applied to volatile variables. The obvious
>way to achieve this would be using SWP,
How? Sorry to disappoint, but the SWP instruction (as its mnemonic
suggests) implements the swapping of data between memory and
registers, atomically (see below for details). It doesn't implement
atomic register-to-memory operations of any other sort. Regretably,
then, there is no obvious way to implement what Clive requests: the
SWP instruction itself cannot be used to do it.
The nearest thing I can think of is to use SWP to implement
synchronisation interlocking (using spin-locks) around the required
("critical region") code sequences. But this is only applicable for
inter-processor interlocks, it does not prevent interrupts from
getting in in the middle of an operation on a single processor.
If you really want atomic *=, +=, -= etc, you would need to add new
"atomic {multiply,add,subtract,<whatever>} register-to-memory"
instructions to ARM to implement them. This is not going to happen
unless some very large customer approaches ARM Ltd with a very large
lump of money and seriously subverts their dedication to the RISC
philosophy.
[ For those who don't know, SWP takes three registers (Rd, Rm, Rn) as
operands, and atomically performs the two steps:
Rd := memory[Rn]
memory[Rn] := Rm
Rd and Rm can be different, so it's more general than a swap - it's
really a read-then-write to a single byte or word memory location. At
the internal level the operation cannot be broken up by interrupt,
though it is still subject to address exception or data abort faults.
External atomicity is effected if appropriate (e.g. in multi-processor
systems) by asserting a LOCK pin on the processor chip for the whole
duration of the read-then-write operations. ]
Mark.
Technical Details
Message-ID:
<19034@acorn.co.uk>Path:
arc1-ca.pugleaf.net!sparky!uunet!mcsun!uknet!acorn!markReferences:
<1992Sep29.160306.6352@infodev.cam.ac.uk>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!uknet!acorn!mark From: mark@acorn.co.uk (Mark Taunton) Newsgroups: comp.sys.acorn.tech Subject: Re: 'volatile' in Norcroft/Acorn C Message-ID: <19034@acorn.co.uk> Date: 30 Sep 92 13:11:12 GMT References: <1992Sep29.160306.6352@infodev.cam.ac.uk> Organization: Acorn Computers Ltd, Cambridge, UK Lines: 45