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Article #643ARM3 cache control in RISC OS 3.10
From: Steve Loft
Date: Tue, 15 Dec 1992 18:26
Date: Tue, 15 Dec 1992 18:26
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831 bytes
Since RISC OS 3.10 has support for the ARM 3, I assume there are some SWI's for controlling the cache? If so, could someone please post (or mail me) the details? Steve -- | Steve Loft steve@klaatu.demon.co.uk | | Doncaster, | | South Yorks. |
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Newsgroups: comp.sys.acorn.tech From: steve@klaatu.demon.co.uk (Steve Loft) Path: arc1-ca.pugleaf.net!sparky!uunet!pipex!demon!klaatu.demon.co.uk!steve Subject: ARM3 cache control in RISC OS 3.10 Reply-To: steve@klaatu.demon.co.uk Distribution: world X-Mailer: cppnews $Revision: 1.20 $ Organization: home Lines: 9 Date: Tue, 15 Dec 1992 18:26:41 +0000 Message-ID: <724469201snx@klaatu.demon.co.uk> Sender: usenet@demon.co.uk