🚀 go-pugleaf

Hello,

   Where processing has a high cache hit-rate the speed should
   be that much quicker (ie, 10Mhz worth of more instructions 
   processed).  However, a problem occurs due to the memory 
   speed. Imagine, the memory bus is a highway with processor 
   access as a filter road.  Most other traffic has priority.
   The A400/1 has a two lane highway, the A5000 has a three lane
   highway.  So when the A400/1 has a traffic jam, the A5000
   has only hit 66% capacity and so the processor can still 
   access memory for whatever it needs.

   Sorry if this is too simplistic but I do like the analogy.

          Jason.H.