Article View: comp.sys.acorn.tech
Article #747Re: ARM risc speed?
From: S.P.Thomas
Date: Sat, 23 Jan 1993 12:11
Date: Sat, 23 Jan 1993 12:11
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3057 bytes
In article <1993Jan21.114022.5930@cs.nott.ac.uk> smb@cs.nott.ac.uk (Simon Burrows) writes:
>A while ago Acorn sent out some guidelines on code sequences which should
>no longer be used if compatibility with future processors is to be maximised.
>They were issued before the ARM250 was brought out, so probably apply to that?
>The problem is that such things are only deemed to be of interest to
>registered developers!
Well, I'm not a registered developer, but I am very interested in this,
as I've built an, um "experimental" lazy functional language compiler
that generates ARM assembler as its target code. I don't use any
kind of NOP instructions, but I would like to know if I'm doing anything
else naughty.
In a similar vain, one of the optimisations I do is to cause the
code to be generated such that the starting addresses of the
code sequences that can be jumped to are aligned to have an address
of &XXXXXX4. This maximises the number of consequtive (sp?) sequential
memory cycles when using MEMC1a. I have three main questions.
1) The effect of this alignment is quite significant on an ARM2
machine. Would the effect be as significant on an ARM3 (or ARM250,
although I suspect the answer is yes, in this case)?
2) In the next generation of memory controllers, are different rules
likely to apply? If so (I suspect this is highly likely), can anyone
give me an idea what they might be?
3) Is it possible that certain orderings of instructions are "better"
than others (ie, faster), even though they achieve the same effect? For
example
ADR ad1,blk1 ADR ad1,blk1
LDMIA ad1,{r0-r7} compared ADR ad2,blk2
ADR ad1,blk2 with LDMIA ad1,{r0-r7}
STMIA ad1,{r0-r7} STMIA ad2,{r0-r7}
These sort of sequences occur a great deal in the code I'm generating.
If there is a difference, what are the rules?
Keep well,
Stephen Thomas
P.S. while I'm currently at the University of Kent, I will be very
shortly (in about a week!) be moving to the University of Nottingham.
My account here should still be active for a while, though.
--
| "You've been having a nightmare. | Stephen Thomas -------------------------|
| And it's not over yet." | Computing Lab, University of Kent, |
| -- Roger Waters, "The Pros and | Canterbury CT2 7NF, UK |
| Cons of Hitchhiking" | Tel: +44 (0)227 764000 x 7754 |
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Path: arc1-ca.pugleaf.net!sparky!uunet!pipex!warwick!uknet!rook.ukc.ac.uk!eagle.ukc.ac.uk!spt1 From: spt1@ukc.ac.uk (S.P.Thomas) Newsgroups: comp.sys.acorn.tech Subject: Re: ARM risc speed? Message-ID: <2804@eagle.ukc.ac.uk> Date: 23 Jan 93 12:11:11 GMT References: <1993Jan20.151326.23097@infodev.cam.ac.uk> <1993Jan20.163935.29452@dcs.warwick.ac.uk> <1993Jan21.114022.5930@cs.nott.ac.uk> Reply-To: spt1@ukc.ac.uk (Stephen Thomas) Organization: Computing Lab, University of Kent at Canterbury, UK. Lines: 51 Nntp-Posting-Host: eagle.ukc.ac.uk