🚀 go-pugleaf

In article <2804@eagle.ukc.ac.uk>, spt1@ukc.ac.uk (S.P.Thomas) writes:
|>....
|> In a similar vain, one of the optimisations I do is to cause the
|> code to be generated such that the starting addresses of the
|> code sequences that can be jumped to are aligned to have an address
|> of &XXXXXX4.  This maximises the number of consequtive (sp?) sequential
|> memory cycles when using MEMC1a.  I have three main questions.
|> 
|> 1) The effect of this alignment is quite significant on an ARM2
|> machine.  Would the effect be as significant on an ARM3 (or ARM250,
|> although I suspect the answer is yes, in this case)?

Yes, very - the ARM3 fetches stuff into the cache 4 words at a time!

 
|> 2) In the next generation of memory controllers, are different rules
|> likely to apply?  If so (I suspect this is highly likely), can anyone
|> give me an idea what they might be?

Very likely.  Don't know any details however.  ARM ltd might be able to help
you on that one, I would guess that information on the Arm610 is available..


|> 3) Is it possible that certain orderings of instructions are "better"
|> than others (ie, faster), even though they achieve the same effect?  For
|> example
|> 
|>         ADR    ad1,blk1                    ADR    ad1,blk1
|>         LDMIA  ad1,{r0-r7}   compared      ADR    ad2,blk2
|>         ADR    ad1,blk2        with        LDMIA  ad1,{r0-r7}
|>         STMIA  ad1,{r0-r7}                 STMIA  ad2,{r0-r7}
|> 
|> These sort of sequences occur a great deal in the code I'm generating.
|> If there is a difference, what are the rules?

The rule is to run both and time them.  :-)


Ian Griffiths