🚀 go-pugleaf

> This means you have to take a 3.579 MHZ signal and generate a 28.63
> MHZ clock from it. To do this you need some sort of PLL. I put one
> together using a NE564, but despite days of work, I could never get it
> to lock on to 28 MHZ. Despite my center freq setting, it insisted on
> remaining unlocked or locking on to 14 MHZ.
> 	Steve Ludtke

It is hard to tell from your description, but it looks like you were
not using the best design for a frequency muliplier.


	   --------------   -------
3.579MHz >-|		|   |	  |
	   | phase/freq |   | VCO |
	   | difference |-->|     |---o------------------> 3.579MHz * N
	-->|		|   |	  |   |
	|  --------------   -------   |   ----------
	|			      |   |	   |
	|			      --->| divide |---
	|				  |  by N  |  |
	|				  |	   |  |
	|				  ----------  |
	|					      |
	-----------------------------------------------

For N=8, the output frequency will be 28.63MHz.  The VCO should be
centered on 28MHz with a narrow capture range if you can arrange it.
The phase/freq block should have a good low pass filter for stability.
The divider is a simple digital divider consisting of three
flip-flops.  A ripple divider will do.
--
	Charles Brown	charles@cv.hp.com or charles%hpcvca@hplabs.hp.com
			or hplabs!hpcvca!charles or "Hey you!"
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