Article View: comp.sys.amiga.tech
Article #10849Re: Math Chip Interface
From: Dale Luck
Date: Fri, 06 Jan 1989 22:43
Date: Fri, 06 Jan 1989 22:43
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In article <256@csd4.milw.wisc.edu> trantow@csd4.milw.wisc.edu (Jerry J Trantow) writes:
>[Eat this ]
>
>Could someone please explain how the IEEE libraries are implemented and
>how operation differs with an 881 or 020.
The 1.3 ieee libraries use 2 different methods when talking to an 881.
If there is an 020/881 set up as a coprocessor the ieee libraris use
the F-line instructions.
If there is 680x0 and an 881 as a memory mapped io device then the ieee
libraries will talk to the chip as a peripheral device spoon feeding
and extracting the numbers.
--
Dale Luck GfxBase/Boing, Inc.
{uunet!cbmvax|pyramid}!amiga!boing!dale
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!attcan!uunet!tank!mimsy!dftsrv!ames!oliveb!amiga!boing!dale From: dale@boing.UUCP (Dale Luck) Newsgroups: comp.sys.amiga.tech Subject: Re: Math Chip Interface Keywords: Coprocessor, Macro, Trap Message-ID: <578@boing.UUCP> Date: 6 Jan 89 22:43:43 GMT References: <255@csd4.milw.wisc.edu> <256@csd4.milw.wisc.edu> Reply-To: dale@boing.UUCP (Dale Luck) Distribution: comp.sys.amiga.tech Organization: Boing, Milpitas, Ca. Lines: 16