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Article #1340

Re: State of PD system enhancement (was: Two Amigas)

#1340
From: Dave Haynie
Date: Tue, 19 Sep 1989 16:21
43 lines
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in article <33.filbo@gorn.santa-cruz.ca.us>, filbo@gorn.santa-cruz.ca.us (Bela Lubkin) says:
> X-Claimer: I >am< R Pentomino!

> This doesn't solve the memory problem on the 2nd machine; perhaps the VM
> routines discussed by -- I forget his name -- in an article titled
> something like "Exit with a bang!"?  (Aside: I never saw even a single
> reply to that message.  Did everyone assume it was a hoax?  Was it old hat?
> I was expecting a flurry of discussion.)

There was LOTS of VM discussion around here back around June or so.  I guess
that someone has it working to a degree by now isn't that amazing, at least
if you were tuned into the earlier discussion.  Of course, the idea of some
kind of VM working on an MMU equipped Amiga isn't that big an issue -- I would
guess anyone with a little OS and MMU programming experience could get 
_something_ working in a week or two of after-hours hacking.  The real test is
how some of the extremely sticky issues (start with "I get a page fault while
I'm Disabled()" and take it from there) are handled.

> IF it takes about the same amount of effort to send a BYTE down the
> parallel port as a BIT down the serial port, shouldn't the limit be
> around 56Kb/sec?

There's a fixed hardware limit at work -- how fast can you talk to the I/O
chips.  The parallel port is based on an 8520 CIA chip; it takes roughly
10 7.16MHz clocks to write one byte to this chip.  The serial port is part
of the Paula chip; as long as you're not letting the blitter steal cycles,
it usually takes 4 7.16MHz clocks to write one byte to this chip.  You'll
have to work some kind of handshaking into the parallel transfer as well.
So from the CPU point of view alone, the CIA takes at least 5x as long to 
send a byte as the serial port.  Now, the serial port isn't going to
shift out that byte in one bus cycle, but it also doesn't occupy the CPU while
it's shifting and all.  The serial speed, then, will be bound by the speed
of Paula's shift register and the quality of the transmission line.  The
parallel port speed will be bound by the speed of CPU writes, your handshaking
mechanism, the quality of its transmission line.

> Bela Lubkin     * *   filbo@gorn.santa-cruz.ca.us   CIS: 73047,1112
>      @        * *     ...ucbvax!ucscc!gorn!filbo    ^^^  REALLY slow [months]
> R Pentomino     *     Filbo @ Pyrzqxgl (408) 476-4633 & XBBS (408) 476-4945
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
                    Too much of everything is just enough
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!ginosko!usc!apple!oliveb!amiga!cbmvax!daveh
References: <33.filbo@gorn.santa-cruz.ca.us>

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!ginosko!usc!apple!oliveb!amiga!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga.tech
Subject: Re: State of PD system enhancement (was: Two Amigas)
Message-ID: <7949@cbmvax.UUCP>
Date: 19 Sep 89 16:21:11 GMT
References: <33.filbo@gorn.santa-cruz.ca.us>
Organization: Commodore Technology, West Chester, PA
Lines: 43