Article View: comp.sys.amiga.tech
Article #2261Interrupt vectors in chip memory (Was: Re: Bus Latency)
From: Tom Limoncelli
Date: Mon, 20 Nov 1989 23:13
Date: Mon, 20 Nov 1989 23:13
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In article <8652@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:
> With fast memory and DMA, you only need one cycle to chip memory, at
> worst, to get unrestricted access to fast memory at full bus speeds.
> With CPU driven I/O, you'll need a few cycles, since interrupt
^^^^^^^^^^^^^^^
> vectors are currently stored in chip memory, but it's not that bad.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> Some devices may not work at acceptible rates with hires 4 plane
> overscan screens if you only have chip memory. With a little fast
> memory, there's not a big problem.
This has always irked me. When AmigaDOS added official support for
the 680x0 (where x<>0) chips, I was surprised that they didn't move
the interrupt vectors to fast memory (since the 68010 and up can do
that).
Chip memory is prone to trashing by errant programs (blitter-tricks
gone bad, beginning programmer mistakes, etc.) Might this be a
feature of 1.4? It could be a switch in preferences to keep older
working.
> Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
--
Tom Limoncelli -- limonce@pilot.njin.net Standard Disclaimer
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<Nov.20.18.13.20.1989.14152@pilot.njin.net>Path:
arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!usc!gem.mps.ohio-state.edu!apple!rutgers!njin!limonceReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!usc!gem.mps.ohio-state.edu!apple!rutgers!njin!limonce From: limonce@pilot.njin.net (Tom Limoncelli) Newsgroups: comp.sys.amiga.tech Subject: Interrupt vectors in chip memory (Was: Re: Bus Latency) Message-ID: <Nov.20.18.13.20.1989.14152@pilot.njin.net> Date: 20 Nov 89 23:13:21 GMT References: <329@berlioz.nsc.com> <8652@cbmvax.UUCP> Organization: Drew University/NJIN Lines: 29