🚀 go-pugleaf

>    This is more in the nature of an agreement than a flame, but there
> are circumstatnces where ECC is LESS relaible than no checking
> currently...specifically when speed limits are being pushed.

>     Modern DRAMs are fairly well protected against cosmic ray induced
> errors, and other transients, but if you use ECC circutry, the overall
> reliability of a memory system has to include the possibility that the
> ECC circutry returns the wrong value or (much more common) does not
> assert the correct value soon enough.
	...
If the ECC RAM returns the correct value but too late, it is not
designed correctly.  Part of the task of design is to make sure there
is enough margin.  So you have not demonstrated your point.  What you
have demonstrated is that: Poorly designed ECC RAM is sometimes less
reliable than well designed RAM w/o ECC.  So what.

>     If you have a friend with an IBM compatible with parity ask him
> when he last had a parity error.  My guess is that with 256K or 1 Meg
> parts, it should be significantly less than 1 per Megabyte per year.
> --
> 					Robert I. Eachus

But I agree that a well designed RAM should have few errors.  The
HP9000/350 with 16MB RAM that I use at work has parity.  (Later models
come with ECC.)  It seems to be averaging one parity error every six
months.  For my computer uses that is good.  For life critical uses
that would not be good enough.
--
	Charles Brown	charles@cv.hp.com or charles%hpcvca@hplabs.hp.com
			or hplabs!hpcvca!charles or "Hey you!"
	Not representing my employer.