Article View: comp.sys.amiga.tech
Article #6717Re: Scheduler changed under 2.0?
From: Mark Waggoner
Date: Sat, 17 Nov 1990 00:35
Date: Sat, 17 Nov 1990 00:35
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1383 bytes
In article <2455@wn1.sci.kun.nl> rhialto@cs.kun.nl (Olaf Seibert) writes:
>In article <15887@cbmvax.commodore.com> peter@cbmvax.commodore.com (Peter Cherna) writes:
>> (Each hardware bus error imposes a 1/4 sec pause).
>
>Why does it take so long? You must execute an awful lot of code
>to take 1/4 second.
No code at all gets executed, bus errors are the result of a hardware
timeout. The cpu starts a memory access and, after a while, nobody
responds and a bus error occurs. At least that's my understanding
of the way it works.
--
Mark Waggoner Santa Clara, CA (408) 721-6306 waggoner@dtg.nsc.com
Unofficially representing National Semiconductor Local Area Networks Group
Officially misrepresenting myself.
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!usc!apple!voder!dtg.nsc.com!waggoner From: waggoner@dtg.nsc.com (Mark Waggoner) Newsgroups: comp.sys.amiga.tech Subject: Re: Scheduler changed under 2.0? Message-ID: <219@boombox.nsc.com> Date: 17 Nov 90 00:35:54 GMT References: <90312.082534GIAMPAL@auvm.auvm.edu> <15756@cbmvax.commodore.com> <90316.091455GIAMPAL@auvm.auvm.edu> <1834c248.ARN04024@adspdk.UUCP> <15887@cbmvax.commodore.com> <2455@wn1.sci.kun.nl> Reply-To: waggoner@dtg.nsc.com (Mark Waggoner) Organization: National Semiconductor, Santa Clara Lines: 17